Patents Examined by David E. Graybill
  • Patent number: 10784200
    Abstract: Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Ian D. Melville, Kevin S. Petrarca, Kenneth P. Rodbell
  • Patent number: 10777413
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 15, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yuping Ren, Guoxiang Ning, Haigou Huang, Sunil K. Singh
  • Patent number: 10777417
    Abstract: A dressing device including: a disk that has an opening on an inside, the disk dressing a polishing surface for polishing a substrate; a rotatable holder, the disk being coupled to a lower surface side of the holder, the holder being provided with a first flow passage that passes from a lower surface to an upper surface, the lower surface being inside an outer edge of the opening of the disk; and a housing that is provided with a distance from the upper surface of the holder, the housing being provided with a second flow passage in an interior, the housing being fixed such that an opening of the second flow passage faces the upper surface of the holder, the second flow passage being connected with a supply source and a suction source of process liquid.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: September 15, 2020
    Assignee: EBARA CORPORATION
    Inventor: Hiroyuki Shinozaki
  • Patent number: 10777672
    Abstract: Embodiments of this disclosure are directed to a multi-gate gallium nitride (GaN) transistor and methods of making the same. The multi-gate GaN transistor includes a gallium nitride layer. The GaN transistor includes two or more gate electrodes between a drain electrode and a source electrode. A polarization layer is located between the first gate electrode and the second gate electrode, the polarization layer forming a two dimensional electron gas (2DEG) within the GaN layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10763364
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: September 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Patent number: 10741469
    Abstract: The invention provides a semiconductor device. The semiconductor device includes a gate structure over fin structures arranged in parallel. Each of the fin structures has a drain portion and a source portion on opposite sides of the gate structure. A drain contact structure is positioned over the drain portions of the fin structures. A source contact structure is positioned over the source portions of the fin structures. A first amount of drain via structures is electrically connected to the drain contact structure. A second amount of source via structures is electrically connected to the source contact structure. The sum of the first amount and the second amount is greater than or equal to 2, and the sum of the first amount and the second amount is less than or equal to two times the amount of fin structures.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: MEDIATEK INC.
    Inventors: Hsien-Hsin Lin, Ming-Tzong Yang, Wen-Kai Wan
  • Patent number: 10741669
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over a top of the fin and laterally adjacent sidewalls of the fin. An N-type gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin, the N-type gate electrode comprising a P-type metal layer on the gate dielectric layer, and an N-type metal layer on the P-type metal layer. A first N-type source or drain region is adjacent a first side of the gate electrode. A second N-type source or drain region is adjacent a second side of the gate electrode, the second side opposite the first side.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10734489
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
  • Patent number: 10727313
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10707074
    Abstract: By sequentially performing, a plurality of times, a step of supplying a mixed gas of an organic metal-containing source gas and an inert gas to a process chamber housing a substrate by adjusting a flow velocity of the mixed gas on the substrate to 7.8 m/s to 15.6 m/s and adjusting a partial pressure of the organic metal-containing source gas in the mixed gas to 0.167 to 0.3, a step of exhausting the process chamber, a step of supplying an oxygen-containing gas to the process chamber, and a step of exhausting the process chamber, a metal oxide film is formed on the substrate.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 7, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yoshimasa Nagatomi, Hirohisa Yamazaki
  • Patent number: 10700116
    Abstract: In a back-illuminated solid-state image pickup device, a first group of charge transfer electrodes (vertical shift register) is present in an imaging region, and a second group of charge transfer electrodes (horizontal shift register) is present in a peripheral region around the imaging region. The light incident surface of the semiconductor substrate 4 corresponding to the peripheral region is etched, and an inorganic light shielding substance SH is filled in the etched region. The amount of the inorganic light shielding substance that evaporates and vaporizes under the vacuum environment is extremely small, and the influence on the imaging by the vaporized gas is small.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 30, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Shinya Otsuka, Hisanori Suzuki, Masaharu Muramatsu
  • Patent number: 10700204
    Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 30, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Stanley Seungchul Song, Kern Rim, Da Yang, Peijie Feng
  • Patent number: 10672835
    Abstract: Methods, systems, and devices for a three-dimensional memory array are described. Memory cells may transform when exposed to elevated temperatures, including elevated temperatures associated with a read or write operation of a neighboring cell, corrupting the data stored in them. To prevent this thermal disturb effect, memory cells may be separated from one another by thermally insulating regions that include one or several interfaces. The interfaces may be formed by layering different materials upon one another or adjusting the deposition parameters of a material during formation. The layers may be created with planar thin-film deposition techniques, for example.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Paolo Fantini
  • Patent number: 10658589
    Abstract: An intermediate semiconductor device structure includes a first area including a memory stack area and a second area including an alignment mark area. The intermediate structure includes a metal interconnect arranged on a substrate in the first area and a first electrode layer arranged on the metal interconnect in the first area, and in the second area. The intermediate structure includes an alignment assisting marker arranged in the second area. The intermediate structure includes a dielectric layer and a second electrode layer arranged on the alignment assisting marker in the second area and on the metal interconnect in the first area. The intermediate structure includes a hard mask layer arranged on the second electrode area. The hard mask layer provides a raised area of topography over the alignment assisting marker. The intermediate structure includes a resist arranged on the hard mask layer in the first area.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hao Tang, Michael Rizzolo, Injo Ok, Theodorus E. Standaert
  • Patent number: 10643840
    Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. A layer is selectively formed on the second surface and defects of the layer are formed on the blocking layer. The defects are removed from the blocking layer on the first surface.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 5, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey W. Anthis, Chang Ke, Pratham Jain, Benjamin Schmiege, Guoqiang Jian, Michael S. Jackson, Lei Zhou, Paul F. Ma, Liqi Wu
  • Patent number: 10636653
    Abstract: The process for growing at least one semiconductor nanowire (3), said growth process comprising a step of forming, on a substrate (1), a nucleation layer (2) for the growth of the nanowire (3) and a step of growth of the nanowire (3). The step of formation of the nucleation layer (2) comprises the following steps: deposition onto the substrate (1) of a layer of a transition metal (4) chosen from Ti, V, Cr, Zr, Nb, Mo, Hf, Ta; nitridation of at least a part (2) of the transition metal layer so as to form a transition metal nitride layer having a surface intended for growing the nanowire (3).
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: April 28, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, ALEDIA
    Inventors: Bérangère Hyot, Benoit Amstatt, Marie-Françoise Armand, Florian Dupont
  • Patent number: 10636665
    Abstract: A dressing device including: a disk that has an opening on an inside, the disk dressing a polishing surface for polishing a substrate; a rotatable holder, the disk being coupled to a lower surface side of the holder, the holder being provided with a first flow passage that passes from a lower surface to an upper surface, the lower surface being inside an outer edge of the opening of the disk; and a housing that is provided with a distance from the upper surface of the holder, the housing being provided with a second flow passage in an interior, the housing being fixed such that an opening of the second flow passage faces the upper surface of the holder, the second flow passage being connected with a supply source and a suction source of process liquid.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 28, 2020
    Assignee: EBARA CORPORATION
    Inventor: Hiroyuki Shinozaki
  • Patent number: 10636630
    Abstract: A processing chamber and a processing method for processing a substrate in the processing chamber with thermal control are described herein. The method includes heating a first substrate using a heater apparatus during a first processing operation. The heater apparatus has a first setpoint during at least a first portion of the first processing operation. The first substrate is disposed on a substrate support surface of an electrostatic chuck in a processing chamber. The method further includes determining a first parameter change corresponding to a resistivity change in the electrostatic chuck, determining a second setpoint for the heater apparatus based on the first parameter change, and controlling the heater apparatus to the second setpoint.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Hemant P. Mungekar, Ganesh Balasubramanian, Yoichi Suzuki, Abdul Aziz Khaja
  • Patent number: 10629485
    Abstract: A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the component. The component comprises at least one recess is formed in the region of the edges bounding the underside; and in that the recess is covered with an insulating layer. A method for the manufacture of such a component comprises the formation of corresponding recesses.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 21, 2020
    Assignee: Vishay Semiconductor GmbH
    Inventor: Claus Mähner
  • Patent number: 10622339
    Abstract: A micro-LED macro transfer method, a micro-LED display device, and a method for fabricating the same are provided. In the micro-LED macro transfer method, the LED chips on an array are divided into a first plurality of LED chips and a second plurality of LED chips. An LED chip includes a first surface and a second surface. The first plurality of LED chips are configured so that their first surfaces are coupled to the first transfer substrate. The second plurality of LED chips are configured so that their second surfaces are coupled to the second transfer substrate. Accordingly, the first transfer substrate transfers the first plurality of LED chips to the first transfer substrate while the second transfer substrate transfers the second plurality of LED chips to the second transfer substrate.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 14, 2020
    Assignee: Xiamen Changelight Co., Ltd.
    Inventors: Zhiwei Lin, Qunxiong Deng, Kaixuan Chen, Zhijie Ke, Xiangjing Zhuo