Patents Examined by David E. Graybill
  • Patent number: 10243176
    Abstract: A method for repairing a bank during manufacture of an organic EL display device when a bank defect portion is produced due to collapsing of a bank, a foreign particle, or the like. The method includes: detecting a defect portion of a lengthwise bank formed over a ground substrate; and when a defect portion is detected, forming, in each of adjacent concave spaces between which the lengthwise bank having the defect portion is located, a dam partitioning the concave space into a first space in a vicinity of the bank defect portion and a second portion not in the vicinity of the bank defect portion. The shape of the dam is configured so that in ejecting organic functional layer ink in each concave space with a nozzle head, there is an ink dropping point in each of the first space and the second space.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: March 26, 2019
    Assignee: JOLED INC.
    Inventors: Yoshiki Hayashida, Kazuhiro Kobayashi, Toshiaki Onimaru, Takayuki Shimamura
  • Patent number: 10236224
    Abstract: An apparatus and a method for reducing wafer warpage are provided. The method includes positioning a mold wafer structure on a stage. The mold wafer structure includes a mold layer and a stack structure positioned on a wafer. The stage includes a center region and an edge region adjacent the center region. Warpage information of the mold wafer structure is obtained. The mold wafer structure is heated by the stage based on the warpage information to reduce a warpage of the mold wafer structure. A temperature of the center region and a temperature of the edge region are different from each other. An operation test is performed on the stack structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Chang Ho Kim
  • Patent number: 10229978
    Abstract: A semiconductor device includes a substrate, an active layer, a source electrode, a drain electrode, a p-type doped layer, a gate electrode, a passivation layer, and a field plate. The active layer is disposed on the substrate. The source electrode, the drain electrode and the p-type doped layer are disposed on the active layer. The p-type doped layer is disposed between the source electrode and the drain electrode, and has a first thickness. The gate electrode is disposed on the p-type doped layer. The passivation layer covers the gate electrode and the active layer. The field plate is disposed on the passivation layer and is electrically connected to the source electrode. The field plate includes a field dispersion portion disposed between the gate electrode and the drain electrode. The passivation layer between the field dispersion portion and the active layer has a second thickness smaller than the first thickness.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 12, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Wen-Chia Liao
  • Patent number: 10217681
    Abstract: Silicon nitride plasma etching processes are disclosed that minimize the SiN roughness layer on a substrate having a SiN layer thereon by simultaneously introducing an oxidizer at a predetermined flow rate and an etch gas into a plasma reaction chamber containing the substrate. The etch gas has the formula CxHyFz, wherein x is 2-5, z is 1 or 2, 2x+2=y+z, and a fluorine atom is located on a terminal carbon atom of the etch gas.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 26, 2019
    Assignee: American Air Liquide, Inc.
    Inventors: James Royer, Venkateswara R. Pallem, Rahul Gupta
  • Patent number: 10211206
    Abstract: Methods of connecting a read driver transistor to a PD and PU inverter of a two-port vertical SRAM via a shared GAA or a vertical cross-couple contact between a GAA of the read driver transistor and the bottom source/drain region of the PD and PU inverter and the resulting devices are provided. Embodiments include forming a first PD transistor, a first PU transistor, a second PU transistor, and a second PD transistor over a substrate; forming a first PG transistor and a second PG transistor over the substrate; forming a read transistor and a read driver transistor laterally separated in the first direction over the substrate, the read transistor and the read driver transistor adjacent to the second PG transistor and the first PD transistor, respectively; and connecting the read driver transistor, the first PD transistor, and the first PU transistor.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jerome Ciavatti
  • Patent number: 10211223
    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to a ferroelectric memory device and a method of manufacturing and using the same. In one aspect, a vertical ferroelectric memory device includes a stack of horizontal layers formed on a semiconductor substrate, where the stack of layers includes a plurality gate electrode layers alternating with a plurality of insulating layers. A vertical structure extends vertically through the stack of horizontal layers, where the vertical structure has a vertical channel structure and a sidewall having formed thereon a vertical transition metal oxide (TMO) ferroelectric layer. A memory cell is formed at each of overlapping regions between the gate electrode layers and the vertical channel structure.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 19, 2019
    Assignee: IMEC vzw
    Inventors: Jan Van Houdt, Pieter Blomme
  • Patent number: 10211727
    Abstract: A voltage multiplier circuit operates in response to a received clock signal to perform a voltage multiplication operation on an input voltage to generate an output voltage. The voltage multiplier circuit includes a pair of intermediate nodes that are capacitively coupled to receive, respectively, opposite phases of a clock signal. A first CMOS driver circuit is coupled to one of the intermediate nodes and has an output configured to generate one phase of a level shifted output clock signal. A second CMOS driver circuit is coupled to another one of the intermediate nodes and has an output configured to generate another phase of the level shifted output clock signal.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 19, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Vikas Rana
  • Patent number: 10204535
    Abstract: Provided is a display device whose display region can be maximized. The display device includes the display region and a terminal electrode. The terminal electrode overlaps with the display region and is electrically connected to an external electrode on a non-display surface of the display region.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10204799
    Abstract: A method for manufacturing a field-effect transistor includes forming an active layer of an oxide semiconductor, forming a conducting film to cover the active layer, patterning the conducting film through an etching process using an etchant to form a source electrode and a drain electrode, and performing, at least before the patterning the conducting film, a treatment on the active layer so that an etching rate of the active layer is less than an etching rate of the conducting film.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 12, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Minehide Kusayanagi, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Ryoichi Saotome, Sadanori Arae
  • Patent number: 10199319
    Abstract: A printed circuit board (PCB) includes a substrate base including at least two chip attach regions spaced apart from one another, a plurality of upper pads disposed in the at least two chip attach regions of the substrate base, an accommodation cavity overlapping a part of each of the at least two chip attach regions and recessed in an upper surface of the substrate base, and at least one spacing groove recessed in the upper surface of the substrate base. The at least one spacing groove is connected to the accommodation cavity, and extends in a region between the at least two chip attach regions.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Bo Shim, Sang-Uk Han, Yun-Seok Choi, Ji-Hwang Kim
  • Patent number: 10192801
    Abstract: A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: January 29, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Jianmin Fang, Kang Chen, Haijing Cao
  • Patent number: 10192785
    Abstract: Devices and methods related to fabrication of shielded modules. In some embodiments, a carrier assembly can be provided for processing of packaged modules. The carrier assembly can include a plate having a first side that defines a plurality of openings, and an adhesive layer implemented on the first side of the plate. The adhesive layer can define a plurality of openings arranged to substantially match the openings of the plate, with each opening of the adhesive layer being dimensioned such that the adhesive layer is capable of providing an adhesive engagement between an underside perimeter portion of a package and a perimeter portion about the corresponding opening of the first side of the plate.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 29, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Yi Liu, Anthony James Lobianco, Matthew Sean Read, Hoang Mong Nguyen, Howard E. Chen
  • Patent number: 10170731
    Abstract: A mask for forming a pattern on a substrate is provided. The mask includes an anodic oxide film formed by anodizing metal, at least one transmission hole configured to vertically penetrate the anodic oxide film and formed in a corresponding relationship with the pattern, a plurality of pores formed in the anodic oxide film so as to have a smaller diameter than the transmission hole, and a magnetic material provided in each of the pores.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: January 1, 2019
    Assignee: Point Engineering Co., Ltd.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun
  • Patent number: 10128440
    Abstract: A deposition mask assembly includes a frame including a first opening portion and a second opening portion spaced apart from each other in a first direction, a first split mask group including a plurality of first split masks arranged on the first opening portion in a second direction crossing the first direction, and a second split mask group including a plurality of second split masks arranged on the second opening portion in the second direction, wherein a boundary between adjacent first split masks in the second direction and a boundary between adjacent second split masks in the second direction are at different positions.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Hwan Lee, Eun Ho Kim
  • Patent number: 10121875
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10121882
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10103117
    Abstract: Provided is a method of manufacturing a fan-out type wafer level package. The method includes forming a fiducial mark pattern on a frame, attaching a semiconductor die to the frame with respect to the fiducial mark pattern, encapsulating the semiconductor die with a passivation layer, for reconstituting the semiconductor die as a wafer level, and sequentially forming a metal seed layer, a redistribution layer, an under bump metal (UBM) seed layer, an UBM layer, and a solder ball on a bonding pad of the semiconductor die upward exposed by an opening region of the passivation layer to finish a fan-out type wafer level package.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: October 16, 2018
    Assignee: SFA Semicon Co., Ltd.
    Inventors: Hyun Hak Jung, Eun Dong Kim, Jong Won Lee, Jai Kyoung Choi, Byeong Ho Jeong
  • Patent number: 10103195
    Abstract: A pixel comprises three adjacent sub-pixels, formed by respective stacks of semi-conducting layers wherein: each sub-pixel comprises a first active layer, adapted for emitting a light at a first wavelength when an electric current passes through it; another sub-pixel comprises a second active layer, adapted for emitting a light at a second wavelength greater than the first wavelength; another sub-pixel comprises a third active layer, adapted for emitting a light at a third wavelength greater than the first wavelength and different from the second wavelength; at least one from among the second and third active layers being adapted for emitting light when it is excited by the light at the first wavelength emitted by the first active layer of the same sub-pixel. Semi-conducting structure and methods for the fabrication of such a pixel are provided.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 16, 2018
    Assignee: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Benjamin Damilano, Jean-Yves Duboz
  • Patent number: 10103278
    Abstract: A method to integrate a vertical IMPATT diode in a planar process.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 16, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiaochuan Bi, Tracey L. Krakowski, Doug Weiser
  • Patent number: 10068918
    Abstract: An integrated circuit is provided including a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells, each cell having a transistor device, formed over the buried oxide layer, a plurality of gate electrode lines running through the cells and providing gate electrodes for the transistor devices of the cells, and a plurality of tap cells configured for electrically contacting the semiconductor bulk substrate and arranged at positions different from positions below or above the plurality of cells having the transistor devices.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 4, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Christian Haufe, Ingolf Lorenz, Michael Zier, Ulrich Gerhard Hensel, Navneet Jain