Patents Examined by David E. Graybill
  • Patent number: 9887328
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a sealing member configured to cover a lower surface of the semiconductor layer and a side surface of the semiconductor layer to protrude to be higher than an upper surface of the semiconductor layer at a side of the semiconductor layer, a fluorescer layer provided above the semiconductor layer and the sealing member, and an insulating film provided between the sealing member and the semiconductor layer and between the sealing member and the fluorescer layer. A corner of a protruding portion of the sealing member is rounded.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Tomizawa, Akihiro Kojima, Miyoko Shimada, Yosuke Akimoto, Hideko Mukaida, Mitsuyoshi Endo, Hideto Furuyama, Yoshiaki Sugizaki, Kazuo Fujimura, Shinya Ito, Shinji Nunotani
  • Patent number: 9881947
    Abstract: An array substrate and a manufacturing method thereof, comprising a base substrate, and a gate, a gate insulating layer, an active layer and a source/drain arranged on the base substrate, the array substrate further comprising an antenna for receiving and/or transmitting wireless signals, the antenna being arranged on the base substrate. By arranging the antenna on the base substrate of the array substrate, the antenna is integrated directly in the display panel. Thus, not only the area of the PCB circuit board in the display device can be reduced, but also the spare area in the array substrate can be utilized sufficiently, thereby improving the integration level of the display device and reducing the total volume of the display device.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: January 30, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY GROUP CO., LTD.
    Inventors: Zongze He, Jianming Wang, Zhiming Meng, Weihao Hu
  • Patent number: 9881842
    Abstract: A first and second vertical fin are formed on a substrate structure. A dielectric layer is disposed on the substrate structure and the first and second vertical fins. A work function metal (WFM) layer is disposed on the dielectric layer. A first sidewall spacer and a second sidewall space are formed proximate to the first vertical fin and the second vertical fin, respectively. A lithographic mask is applied to a first area proximate to the first vertical fin including the first vertical fin, and a portion of the WFM layer proximate to the first vertical fin. A portion of the WFM layer proximate to the second sidewall spacer is recessed below an upper surface of the second sidewall spacer. The lithographic mask is removed. A portion of the dielectric layer is removed to produce a wimpy vertical transport device and a nominal vertical transport device on the substrate structure.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: January 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Su Chen Fan, Catherine B. Labelle, Xin Miao
  • Patent number: 9842922
    Abstract: A transistor includes a III-N layer structure comprising a III-N channel layer between a III-N barrier layer and a p-type III-N layer. The transistor further includes a source, a drain, and a gate between the source and the drain, the gate being over the III-N layer structure. The p-type III-N layer includes a first portion that is at least partially in a device access region between the gate and the drain, and the first portion of the p-type III-N layer is electrically connected to the source and electrically isolated from the drain. When the transistor is biased in the off state, the p-type layer can cause channel charge in the device access region to deplete as the drain voltage increases, thereby leading to higher breakdown voltages.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: December 12, 2017
    Assignee: Transphorm Inc.
    Inventors: Umesh Mishra, Rakesh K. Lal, Stacia Keller, Srabanti Chowdhury
  • Patent number: 9831354
    Abstract: Split-gate flash memory and forming method thereof are provided. The method includes: forming a first dielectric layer on a semiconductor substrate; forming a floating gate layer on the first dielectric layer; forming a mask layer on the floating gate layer; etching the mask layer until first groove exposing the floating gate layer is formed; forming a protective sidewall on sidewall of the first groove; forming a gate dielectric layer on bottom and the sidewall of the first groove; forming two control gates on the gate dielectric layer, the remained first groove serving as second groove; etching the gate dielectric layer and the floating gate layer at bottom of the second groove until third groove exposing the first dielectric layer is formed; forming a source in the semiconductor substrate under the third groove; and forming a second dielectric layer in the third groove. Reliability and durability of the memory are improved.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 28, 2017
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Binghan Li
  • Patent number: 9805934
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chung Jen, Yu-Hua Yen
  • Patent number: 9793256
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: October 17, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 9786748
    Abstract: A CZ silicon ingot is doped with donors and acceptors and includes an axial gradient of doping concentration of the donors and of the acceptors. An electrically active net doping concentration, which is based on a difference between the doping concentrations of the donors and acceptors varies by less than 60% for at least 40% of an axial length of the CZ silicon ingot due to partial compensation of at least 20% of the doping concentration of the donors by the acceptors.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Nico Caspary, Hans-Joachim Schulze
  • Patent number: 9773895
    Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 26, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Balaji Padmanabhan, Prasad Venkatraman, Peter Moens, Mihir Mudholkar, Joe Fulton, Philip Celaya, Stephen St. Germain, Chun-Li Liu, Jason McDonald, Alexander Young, Ali Salih
  • Patent number: 9773906
    Abstract: Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wei-E Wang, Mark S. Rodder, Ganesh Hedge, Christopher Bowen
  • Patent number: 9768124
    Abstract: A semiconductor package having a second semiconductor package or module integrated therein. The semiconductor package of the present invention typically comprises active and passive devices which are each electrically connected to an underlying substrate. The substrate is configured to place such active and passive devices into electrical communication with contacts of the substrate disposed on a surface thereof opposite that to which the active and passive devices are mounted. The module of the semiconductor package resides within a complimentary opening disposed within the substrate thereof. The module and the active and passive devices of the semiconductor package are each fully or at least partially covered by a package body of the semiconductor package.
    Type: Grant
    Filed: September 11, 2016
    Date of Patent: September 19, 2017
    Assignee: Amkor Technology, Inc.
    Inventors: Christopher M. Scanlan, Christopher J. Berry
  • Patent number: 9748106
    Abstract: A method for fabricating a semiconductor package, the method includes forming at least one conductive via having a first end and a second end opposite the first end in a wafer, in which the wafer has a first surface and a second surface opposite the first surface, and the first end of the at least one conductive via is exposed of the first surface of the wafer; grinding the second surface of the wafer to form an inner portion and a ring portion surrounding the inner portion of the wafer, wherein the inner portion has a thinner thickness than that of the ring portion; and etching the inner portion to expose the second end of the at least one conductive via.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 29, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yi-Jen Lo, Neng-Tai Shih
  • Patent number: 9741817
    Abstract: A method for manufacturing a metal insulator metal (MIM) trench capacitor, the method may include forming a cavity in an Intermetal Dielectric stack, wherein a bottom of the cavity exposes a lower metal layer; wherein the Intermetal Dielectric stack comprises a top dielectric layer; depositing a first metal layer on a bottom of a cavity and on sidewalls of the cavity; depositing a sacrificial layer over the first metal layer; filling the cavity with a filling material; removing, by a planarization process, a portion of the sacrificial layer positioned above the top dielectric layer and a portion of the first metal layer positioned above the top dielectric layer to expose an upper portion of the sacrificial layer and an upper portion of the first metal layer; forming a recess by removing the upper portion of the sacrificial layer and the upper portion the first metal layer while using the filling material as a mask; removing the filling material by a first removal process that is selective to the sacrificial l
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: August 22, 2017
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Michael Lisiansky, Amos Fenigstein, Yakov Roizin, Hironori Matsuyoshi, Toshiaki Ohmi
  • Patent number: 9721919
    Abstract: Solder-bumped semiconductor substrates (e.g., semiconductor wafers) and methods for forming solder bumped semiconductor substrates are provided, in which solder bumps are formed on a semiconductor substrate using preformed solder balls having different compositions and/or sizes. Two or more solder balls masks are successively utilized to place different types of preformed solder balls (differing in composition and/or size) into corresponding cavities of a solder ball fixture, and thereby form an array of different types of preformed solder balls arranged in the solder ball fixture. The array of preformed solder balls in the solder ball fixture are then transferred to corresponding contact pads of a semiconductor substrate (e.g., semiconductor wafer) using a single solder reflow process. This process allows different types of preformed solder bumps to be bonded to a semiconductor substrate at the same time using a single solder reflow process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventor: Jae-Woong Nah
  • Patent number: 9721812
    Abstract: A method for fabricating an optical multi-chip module (MCM) includes temporarily curing an underfill material on a chip including an optical device to prevent flow of the underfill material. The chip is flip-chip mounted on a waveguide module having a mirror for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module. The underfill material is cured to adhere the chip to the waveguide module.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Akihiro Horibe, Masao Tokunari
  • Patent number: 9721905
    Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju Yamada, Takashi Yamazaki, Masatoshi Fukuda, Yasuhiro Koshio
  • Patent number: 9704885
    Abstract: A pixel structure, an array substrate and a display device. The pixel substrate comprises a first pixel electrode and a second pixel electrode arranged in a first direction, and a thin film transistor (TFT) disposed between the first pixel electrode and the second pixel electrode. The TFT includes a comb-shaped source, a comb-shaped first drain and a comb-shaped second drain; and a channel region of the TFT is defined by the comb-shaped source respectively and the comb-shaped first drain and the comb-shaped second drain. The channel region has a greater ratio of width to length, thus improving the driving capability of the TFT for driving the first pixel electrode and the second pixel electrode.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: July 11, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Pan Li, Wenbo Li, Yong Qiao, Hongfei Cheng, Jianbo Xian
  • Patent number: 9698175
    Abstract: An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: July 4, 2017
    Assignee: Shenzhen China Star Optoelectionics Technology Co., Ltd
    Inventor: Dongzi Gao
  • Patent number: 9691684
    Abstract: An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hwa Park, Sung-hee Kang, Kwang-jin Moon, Byung-lyul Park, Suk-chul Bang
  • Patent number: 9691726
    Abstract: A method includes forming a first composite wafer including molding a plurality of device dies and a plurality of through-vias in a first molding material, and forming redistribution lines on opposite sides of the first molding material. The redistribution lines are inter-coupled through the plurality of through-vias. The method further includes forming a second composite wafer including stacking a plurality of dies to form a plurality of die stacks, and molding the plurality of die stacks in a second molding material. The second molding material fills gaps between the plurality of die stacks. The first composite wafer is bonded to the second composite wafer to form a third composite wafer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsien-Wei Chen, Cheng-Lin Huang, Meng-Tse Chen, Chung-Shi Liu