Patents Examined by David E. Graybill
  • Patent number: 9660046
    Abstract: A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: May 23, 2017
    Assignees: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO, TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Sachiko Aoi, Yukihiko Watanabe, Katsumi Suzuki, Shoji Mizuno
  • Patent number: 9660159
    Abstract: A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from ?1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 ??·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: May 23, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Keiji Sato, Shunpei Yamazaki
  • Patent number: 9660186
    Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhye Bae, Wonjun Lee, Yoonsung Han, Hoon Han, Kyu-Man Hwang, Yongsun Ko
  • Patent number: 9620433
    Abstract: System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: April 11, 2017
    Assignee: Tessera, Inc.
    Inventor: David Edward Fisch
  • Patent number: 9613816
    Abstract: An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: April 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Chieh Tsai, Tz-Wei Lin, Sheng-Jen Yang, Hung-Yin Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
  • Patent number: 9607986
    Abstract: A method of making a semiconductor device begins with a semiconductor wafer that includes a first semiconductor layer overlying a second semiconductor layer. A first trench is etched in the semiconductor wafer. The first trench is filled with insulating material. A second trench is etched within the first trench and through the insulating material, such that insulating material remains along sidewalls of the first trench. The second trench exposes a portion of the second insulating layer. A semiconductor layer can then be grown within the second trench using the second semiconductor layer as a seed layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jiang Yan, Danny Pak-Chum Shum, Armin Tilke
  • Patent number: 9601417
    Abstract: Various aspects provide for bending a bending a lead frame of a semiconductor device package into a shape of an “L” and mounting the package on a substrate. A horizontal portion of the bent lead-frame is about parallel with a surface of the package. A vertical portion of the bent lead frame is configured to extend the horizontal portion beyond the surface of the package. A device may be mounted between the substrate and the package.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 21, 2017
    Assignee: Unigen Corporation
    Inventors: Hanjoo Na, Santosh Kumar
  • Patent number: 9601386
    Abstract: A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices. and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang
  • Patent number: 9590045
    Abstract: A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 7, 2017
    Assignee: IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ—INSTITUT FUR INNOVATIVE MIKROELEKTRONIK
    Inventors: Andre Wolff, Wolfgang Mehr, Grzegorz Lupina, Jaroslaw Dabrowski, Gunther Lippert, Mindaugas Lukosius, Chafik Meliani, Christian Wenger
  • Patent number: 9583498
    Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Patent number: 9570429
    Abstract: The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: February 14, 2017
    Assignee: SHANGHAI JADIC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jianhong Mao, Fengqin Han, Zhiwei Wang, Wenfen Chang
  • Patent number: 9564079
    Abstract: A flexible display device includes a flexible display panel including: a plastic film; a pixel circuit on the plastic film; a light emitting element; and an inorganic layer. Openings are in the inorganic layer along a cutting line for cutting the flexible display panel.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: February 7, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jun Namkung
  • Patent number: 9559107
    Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: January 31, 2017
    Assignee: International Businesss Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Patent number: 9553116
    Abstract: A substrate-removed, surface passivated, and anti-reflective (AR) coated detector assembly is provided. The assembly has an AR coating or passivation layer which includes a wide bandgap thin-film dielectric/passivation layer integrated therein. The wide bandgap thin-film dielectric/passivation layer is positioned proximal to a back interface of a substrate-removed detector assembly. A method of manufacturing the detector assembly includes etching a backside of a partially-removed-substrate detector assembly to obtain an etched detector assembly removed from a substrate. A wide bandgap layer is deposited, in a vacuum chamber, on the etched detector assembly without utilizing an adhesive layer. Additional anti-reflective coating layers are deposited, in the same vacuum chamber, on the wide bandgap layer to form an anti-reflective coating layer with the wide bandgap layer integrated therein.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 24, 2017
    Assignee: Teledyne Scientific & Imaging, LLC
    Inventors: Donald L. Lee, Eric Piquette, Majid Zandian, Paul H. Kobrin, Haluk Sankur
  • Patent number: 9548313
    Abstract: A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 17, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Shinsuke Yada, Shigehiro Fujino, Hajime Kimura, Masanori Terahara, Ryoichi Honma, Hiroyuki Ogawa, Ryousuke Itou
  • Patent number: 9548199
    Abstract: A method, which forms an air-bubble-free thin film with a high-viscosity fluid resin, initially dispenses the fluid resin on an outer region of a semiconductor wafer while the semiconductor wafer is spinning, and then dispenses the fluid resin onto the center of the semiconductor wafer after the semiconductor wafer has stopped spinning.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: January 17, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sandra Zheng, Mark James Smiley, Douglas Jay Levack, Ronald Dean Powell
  • Patent number: 9540725
    Abstract: Provided is a method of controlling a gas cluster ion beam (GCIB) system for processing structures on a substrate. A GCIB system comprises deflection plates for directing a GCIB towards a substrate, the GCIB system coupled to a substrate scanning device configured to move a substrate in three dimensions. The substrate is exposed to the GCIB while the substrate is being moved by the substrate scanning device. A controller is used to control a set of deflection operating parameters comprising a deflection angle ?, voltage differential of the deflection plates, frequency of the deflection plate power, beam current, substrate distance, pressure in the nozzle, gas flow rate in the process chamber, separation of beam burns, duration of the bean burn, and/or duty cycle of the beam deflector output.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: January 10, 2017
    Assignee: TEL Epion Inc.
    Inventors: Kenneth Regan, Yan Shao, Robert K. Becker, Christopher K. Olsen
  • Patent number: 9530945
    Abstract: An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 27, 2016
    Assignee: Invensas Corporation
    Inventor: Avner Badehi
  • Patent number: 9524869
    Abstract: A nitride-based semiconductor light-emitting device includes a light-emitting stack comprising a first semiconductor structure having a first conductivity, a second semiconductor structure having a second conductivity, and an active region interposed the first semiconductor structure and the second semiconductor structure; a semiconductor buffer structure formed under the first semiconductor structure; and an un-doped AlGaN layer formed between the first semiconductor structure and the semiconductor buffer structure.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: December 20, 2016
    Assignee: Epistar Corporation
    Inventors: Wen Hsiang Lin, Chang-Hua Hsieh
  • Patent number: 9496369
    Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: November 15, 2016
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Man-Tang Wu, Jeng-Wei Yang, Chien-Sheng Su, Chun-Ming Chen, Nhan Do