Abstract: A Scalable Finite Impulse Response (“SFIR”) filter is disclosed. The SFIR filter includes a pre-processing section, a post-processing section, and a finite impulse response (“FIR”) Matrix. The FIR Matrix includes a plurality of filter taps and a plurality of signal paths in signal communication with each filter tap. The plurality of signal paths are arranged to allow re-configurable data throughput between the each filter tap and the pre-processing section and post-processing section are in signal communication with the FIR Matrix.

Abstract: The present disclosure relates to methods and systems for signal processing using coordinate descent technique for solving technical implementation problems that are expressed as unit-modulus least squares (UMLS) and unit-modulus quadratic program (UMQP) problems. Embodiments provide for iteratively minimizing an objective function of a signal vector associated with a UMLS/UMQP problem expression over a set of coordinates of the signal vector to a convergence point. The objective function is minimized with respect to a vector element corresponding to a selected coordinate index, while other vector elements that do not correspond to the selected coordinate index are fixed. Accordingly, at each iteration, minimizing the objective function involves a solution to a one-dimensional univariate quadratic minimization. Embodiments also provide various coordinate index selection rules that include a cyclic CD rule (CCD), a randomized CD rule (RCD), randomly permuted CD rule (RPCD), and a greedy CD rule (CCD).

Abstract: Embodiments of quantum ring oscillator-based coherence preservation circuits including a cascaded set of stages are described. Embodiments of such quantum ring oscillator-based coherence preservation circuits allow the internal (superpositioned) quantum state information of stored qubits to be preserved over long periods of time and present options for the measurement and potential correction of both deterministic and non-deterministic errors without disturbing the quantum information stored in the structure itself.

Abstract: Aspects for converting floating-point numbers in a processor are described herein. As an example, the aspects may include receiving, by a floating-point number converter, an exponent bit length, a base value, and one or more first floating-point numbers of a first bit length. Further, the aspects may include calculating, by the floating-point number converter, one or more second floating-point numbers of a second bit length based on the exponent bit length and the base value, the one or more second floating-point numbers respectively corresponding to the one or more first floating-point numbers.

Abstract: Reduced precision computer number formats inherently limit the quantity of discrete numeric values that can be represented. Therefore, the solution values of an arithmetic function, for each numeric value that is individually and uniquely expressible utilizing such a reduced precision computer number format, can be precomputed since the quantity of unique solution values can be limited to a quantity that can be conveniently stored, such as in an array. Subsequently, rather than computing the solution value of such an arithmetic function, for a given input value, the precomputed array can be referenced and a solution value corresponding to the given input value can be read from the array. Reading numeric values from an array can be substantially faster than computing solution values of a computationally-expensive arithmetic function.

Abstract: An apparatus for determining a similarity information on the basis of one or more input signals is configured to determine a zero crossing information describing a number of zero crossings in a respective portion for a plurality of portions of at least one of the one or more input signals. The apparatus is configured to perform a comparison on the basis of the zero crossing information, in order to determine the similarity information. A method for determining a similarity information and a computer program are also described. Moreover, an apparatus for determining an autocorrelation information and an apparatus for determining a cross-correlation information are based on similar considerations.

Abstract: In various embodiments, a floating-point arithmetic circuit includes a range exception detection circuit and an output circuit. The range exception detection circuit may generate a selection signal that indicates whether a floating-point arithmetic result generated within the floating-point arithmetic circuit is within a specified range. The output circuit may output the floating-point arithmetic result in response to the selection signal indicating the floating-point arithmetic result is within a specified range. The output circuit may output a corresponding specified value in response to the selection signal indicating the floating-point arithmetic result is not within the specified range. Accordingly, floating-point arithmetic operations may be performed in combination with an operation that limits a range of an output to a specified range.

Abstract: Random number generators include a thermal optical source and detector configured to produce random numbers based on quantum-optical intensity fluctuations. An optical flux is detected, and signals proportional to optical intensity and a delayed optical intensity are combined. The combined signals can be electrical signals or optical signals, and the optical source is selected so as to have low coherence over a predetermined range of delay times. Balanced optical detectors can be used to reduce common mode noise, and in some examples, the optical flux is directed to only one of a pair of balanced detectors.

Abstract: A system and method are provided for use with streaming blocks of data, each of the streaming blocks of data including a number bits of data. The system includes a first compressor and a second compressor. The first compressor can receive and store a number n blocks of the streaming blocks of data, can receive and store a block of data to be compressed of the streaming blocks of data, can compress consecutive bits within the block of data to be compressed based on the n blocks of the streaming blocks of data, can output a match descriptor and a literal segment. The match descriptor is based on the compressed consecutive bits. The literal segment is based on a remainder of the number of bits of the data to be compressed not including the consecutive bits. The second compressor can compress the literal segment and can output a compressed data block including the match descriptor and a compressed string of data based on the compressed literal segment.

Abstract: Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

Abstract: Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Abstract: Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits matrix decomposition operations into parallel operation circuits and serial operation circuits, and joins the parallel and serial operation circuits using specific dependency handling logic for efficient parallel execution. This provides fast matrix decomposition with low power consumption, reduced memory footprint, and reduced memory bandwidth.

Abstract: A method for efficient transmission of coefficients examines a coefficient list, presents the coefficients as binary floating point representation, and transmits the list of coefficients as a header having an exponent prefix, a fractional suffix, and each coefficient value as an exponent suffix and fractional prefix. A method for reception of coefficients receives a header including an exponent prefix, a fractional suffix, thereafter receiving each value as a sign bit, an exponent suffix and a fractional prefix, reconstituting an approximation of the original value, in sequence, as a sign bit, exponent prefix exponent suffix, fraction prefix, and fraction suffix, thereby greatly reducing the amount of information to be transmitted or received.

Abstract: Techniques related to matrix multiplication at memory bandwidth are disclosed. Computing device(s) perform multiplication of a first matrix with a second matrix to generate a third matrix. A first register stores contiguous element values of the first matrix. Furthermore, a second register stores a first set of contiguous element values of the second matrix, and a third register stores a second set of contiguous element values of the second matrix. The first set and the second set correspond to a first row and a second row, respectively, of the second matrix. The first row and the second row are contiguous rows. A single instruction is executed to cause at least a partial computation of contiguous element values of the third matrix. The single instruction causes multiplication of element values stored in the first register with element values stored in the second and third registers and grouped accumulation of the products.

Abstract: A matrix computation unit includes a systolic array of cells arranged along a first and second dimension, in which the systolic array of cells includes a first multiple of cells, each cell of the first multiple of cells including: a weight register configured to store a weight input; multiple activation registers, each activation register of the multiple activation registers configured to store a corresponding activation input; multiplexer circuitry communicatively coupled to the multiple activation registers and configured to select, from the multiple activation registers, one of the activation inputs as a selected activation input; and multiplication circuitry communicatively coupled to the weight register and to the multiplexer, in which the multiplication circuitry is configured to output a product of the weight input and the selected activation input.

Abstract: A system includes a processor and a memory. The memory stores instructions executable by the processor to receive sensor data including floating-point numbers. The memory stores instructions to convert the floating-point numbers to integer numbers based on a parameter set. The memory stores instructions to actuate a vehicle component based on the integer numbers.

Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

Abstract: A method for multiplying a first sparse matrix by a second sparse matrix in an associative memory device includes storing multiplicand information related to each non-zero element of the second sparse matrix in a computation column of the associative memory device; the multiplicand information includes at least a multiplicand value. According to a first linear algebra rule, the method associates multiplier information related to a non-zero element of the first sparse matrix with each of its associated multiplicands, the multiplier information includes at least a multiplier value. The method concurrently stores the multiplier information in the computation columns of each associated multiplicand. The method, concurrently on all computation columns, multiplies a multiplier value by its associated multiplicand value to provide a product in the computation column, and adds together products from computation columns, associated according to a second linear algebra rule, to provide a resultant matrix.

Abstract: Embodiments relate to a configurable convolution engine that receives configuration information to perform convolution and other deep machine learning operations on streaming input data of various formats. The convolution engine may include two convolution circuits that each generate a stream of values by applying convolution kernels to input data. The stream of values may each define one or more channels of image data. A channel merge circuit combines the streams of values from each convolution circuit in accordance with a selected mode of operation. In one mode, the first and second streams from the convolution circuits are merged into an output stream having the combined channels of the first and second streams in an interleaved manner. In another mode, the first stream from the first convolution circuit is fed into the input of the second convolution circuit.

Abstract: In one embodiment, a matrix operation may be performed, wherein the matrix operation comprises a matrix multiplication operation on a plurality of matrix operands. Matrix data may be received from a multi-dimensional memory, wherein the matrix data is associated with the plurality of matrix operands. The plurality of matrix operands may be extracted from the matrix data, wherein the plurality of matrix operands comprises a first matrix operand and a second matrix operand. A first transform may be performed on the first matrix operand to obtain a transformed matrix operand, wherein performing matrix multiplication using the transformed matrix operand is faster than performing matrix multiplication using the first matrix operand. Matrix multiplication may be performed on the transformed matrix operand to obtain a partial result. A second transform may be performed on the partial result to obtain a result of the matrix multiplication operation.