Abstract: A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.

Abstract: In one embodiment, a processor comprises a redirect unit configured to detect a match of an instruction pointer (IP) in an IP redirect table, the IP corresponding to a guest instruction that the processor has intercepted, wherein the guest is executed under control of a virtual machine monitor (VMM), and wherein the redirect unit is configured to redirect instruction fetching by the processor to a routine identified in the IP redirect table instead of exiting to the VMM in response to the intercept of the guest instruction.

Abstract: Techniques for allocating work requests to performing centers include generating options for assigning the work requests to the performing centers. The options are based upon predetermined historical factors capturing work request characteristics and performing center characteristics. For each of the options, the work requests are scheduled to determine a corresponding duration of the work requests, and an overall cost is computed. One of the options is selected based on the overall cost and the corresponding duration.

Abstract: A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output.

Abstract: A hardware wake-and-go mechanism is provided for a data processing system. The wake-and-go mechanism looks ahead in the instruction stream of a thread for programming idioms that indicates that the thread is waiting for an event. The wake-and-go mechanism updates a wake-and-go array with a target address associated with the event for each recognized programming idiom. When the thread reaches a programming idiom, the thread goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The wake-and-go mechanism associates these storage addresses with the threads waiting for an event at the target addresses, and may wake the one or more threads waiting for the event.

Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer, detecting the assertion signal in the accelerators and communicating a request for a lock, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer. Other embodiments are described and claimed.

Abstract: Apparatus and methods for quickly switching active context between data pointer registers are disclosed. The apparatus can include a first register operable for storing a first data pointer and a second register operable for storing a second data pointer. A configuration register can provide a first signal specifying either the first or the second data pointer as an active data pointer. An instruction decoder can receive a data pointer instruction and output a second signal. The first and second signals can be independent from one another. Decoding logic coupled to the logic devices can output one of the first or second data pointers as the active data pointer in response to the first and second signals.

Abstract: Measuring processes are started at a plurality of priority levels. A different one of the measuring processes is started for each of the priority levels. Subsequently, for each of the measuring processes, it is determined whether each measuring process is scheduled for executing at a respective target rate. In response to determining that a particular measuring process of the measuring processes is not scheduled for executing at a particular target rate, resource allocation to at least one monitored process running at a particular level of the priority levels is adjusted. The at least one monitored process is not any of the measuring processes.

Abstract: An event processing apparatus has a central processing unit (CPU) and an event queue that temporarily accumulates a plurality of events when occurring. The CPU executes an event queue optimization module for executing filtering processes to delete one or more events based on optimization definition information, and/or for executing chunking processes to integrate a plurality of events into an event, for a plurality of events accumulated in the event queue, based on a CPU load calculation involving the sum of mean CPU-execution-times for unexecuted tasks corresponding to the queued events.

Abstract: A processor blade determines whether a selected processing task is to be off-loaded to a storage blade for processing. The selected processing task is off-loaded to the storage blade via a planar bus communication path, in response to determining that the selected processing task is to be off-loaded to the storage blade. The off-loaded selected processing task is processed in the storage blade. The storage blade communicates the results of the processing of the off-loaded selected processing task to the processor blade.

Abstract: A multi-mode register rename mechanism which allows a simultaneous multi-threaded processor to support full out-of-order thread execution when the number of threads is low and in-order thread execution when the number of threads increases. Responsive to changing an execution mode of a processor to operate in in-order thread execution mode, the illustrative embodiments switch a physical register in the data processing system to an architected facility, thereby forming a switched physical register. When an instruction is issued to an execution unit, wherein the issued instruction comprises a thread bit, the thread bit is examined to determine if the instruction accesses an architected facility. If the issued instruction accesses an architected facility, the instruction is executed, and the results of the executed instruction are written to the switched physical register.

Abstract: An array of processing elements (PEs) is logically twisted in a first direction, wrapped to form a cylindrical array, and grouped in a second direction to determine PEs that are to be located in clusters and implemented to form physical clusters of PEs. Inter-cluster communication paths are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port and a single receive port.

Abstract: A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

Abstract: A system is disclosed for providing branch misprediction prediction in a microprocessor. The system includes a mispredicted branch table that includes address, distance, and true/not true fields, and an index to the mispredicted branch table that is formed responsive to 1) a current mispredicted branch, 2) a global history, 3) a global misprediction history, and 4) a branch misprediction distance.

Abstract: Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer is to store an instruction stream having a single entry point and a single exit point. The dead instruction identifier is to identify dead instructions based on a forward pass through the instruction stream.

Abstract: Automated management of partition service assignment to a virtual input/output (VIO) adapter is provided. Responsive to creation of a new partition service in a data processing system, a partition priority number is determined for the new partition service, and, for each VIO adapter, the partition priority numbers of the partition services currently assigned to that VIO adapter are summed. For a VIO adapter with a lowest sum of partition priority numbers, logic determines whether assigning the new partition service to that VIO adapter results in its summed partition priority number being above a predefined threshold, and the new partition service is assigned to a VIO adapter based, at least in part, on whether assigning the new partition service to the VIO adapter with the lowest sum of partition priority numbers results in that VIO adapter's summed partition priority number exceeding the predefined threshold.

Abstract: An information processing device including registers (105) for holding data and an operation device (102) for executing arithmetic and logic operations on input/output data held in the register. The information processing device can issue an inter-register copy instruction for instructing data held in one register to be copied to another register. The information processing device further includes a copy information holding device (113) for reserving for execution of a data copy operation by the inter-register copy instruction from a control unit (108) so as to execute the actual copy operation simultaneously with the succeeding instruction to hide the execution time of the copy operation. Thus, in the inter-register copy instruction execution phase, a reservation for a data copy operation is stored in the copy information holding device so that the execution phase is completed without performing the actual data copy operation.

Abstract: A processor triggers a first advanced execution processing pass to an instruction sequence in response to a first stalled instruction and initiates execution of a further instruction in the instruction sequence that stalls during the performance of the first advanced execution processing pass. A second advanced execution pass is performed through the instruction sequence in which the further instruction is processed again to provide a valid result after stalling. In one form, the first instruction is performed while the processor operates in a normal execution mode and the first and second advanced execution processing passes are performed while the processor operates in an advance execution mode.