Abstract: A method and system for storage and delivery of a plurality of data files is disclosed. The method and system include dividing at least one data file of the plurality of data files into a plurality of data blocks. The method and system further include storing the at least one data file by storing the plurality of data blocks in a plurality of disks, allowing a user to select any data file of the plurality of data files for delivery, and transferring the selected data file from the plurality of disks. Each disk includes a plurality of blocks having a disk block size. Storing the at least one data file includes storing a data block of the plurality of data blocks in a next available block of one disk, determining a complementary block on a next disk, storing a next data block in the complementary block on the next disk, and repeating the prior two steps for each of the plurality of disks until the at least one data file is stored.

Abstract: A register window file method and apparatus is disclosed. A register file is formed from a plurality of registers. The registers are grouped into a plurality of logical windows. Window selection logic selects among the logical windows and thereby limits access at any given time to the selected logical window. Because access is limited to only one window at a time, an individual register can be selected by specifying its virtual register number. Therefore, there is no need to translate from virtual address numbers to physical address numbers when accessing registers. This means that virtual register number to physical register number translation logic of the prior art is no longer required. Thus, the area on the integrated circuit chip formerly occupied by the translation logic is no longer required. Furthermore, the translation delays per instruction introduced by the translation logic are also eliminated. Moreover, each register only shares read and write lines with the other registers of its window.

Abstract: Apparatus and method for coordinating cache coherency between host cache memories in a distributed information system in a system which comprises at least one main storage memory coupled to a plurality of host computers through controllers. Each host computer includes a host cache controller which maintains the state of the data stored in its associated memory and maintains communicating with a main memory controller for participating in the control of coordinated reading and writing of data between the host cache memories and the main storage memory. The system maintains cache coherency by the exchange of commands between the main memory controller and the hosts cache controllers each of which define the state of the blocks of data stored in the host cache memories.

Abstract: A central processing unit is connected to an external memory including system memory and an external cache. The central processing unit includes a First-In-First-Out (FIFO) load buffer configured to generate an access to the external memory in response to a data prefetch command. The access to external memory has an associated data load latency period as data is moved from the system memory into the external cache. Instead of requiring the access to external memory to be completed before another FIFO load buffer address is processed, as is typically required in a FIFO load buffer configuration, the FIFO load buffer responds to the data prefetch command by processing additional stored addresses during the data load latency period.