Abstract: Provided is a preparation method of a crystalline silicon film.

Abstract: Semiconductor device packages include first and second semiconductor dice in a facing relationship. At least one group of solder bumps is substantially along a centerline between the semiconductor dice and operably coupled with integrated circuitry of the first and second semiconductor dice. Another group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the first semiconductor die. A further group of solder bumps is laterally offset from the centerline and operably coupled only with integrated circuitry of the second semiconductor die. Methods of forming semiconductor device packages include aligning first and second semiconductor dice with active surfaces facing each other, the first and second semiconductor dice each including bond pads along a centerline thereof and additional bond pads laterally offset from the centerline thereof.

Abstract: An embodiment method includes forming a nanowire extending upwards from a substrate, wherein the nanowire includes: a bottom semiconductor region; a middle semiconductor region over the bottom semiconductor region; and a top semiconductor region over the middle semiconductor region. The method also includes forming a dielectric layer around and extending over the nanowire and forming a chemical mechanical polish-stop (CMP-stop) layer within the dielectric layer using an implantation process. After forming the CMP-stop layer, the dielectric layer is planarized.

Abstract: A method for manufacturing a light emitting device, includes a first step of mounting a light emitting element on a support base with a bump; and a second step of clamping the support base and the light emitting element and pressing between a lower molding die and an upper molding die to plastically deform the bump, and injecting the compound of a cover member into a mold cavity between the lower molding die and the upper molding die and curing the compound to form the cover member that covers at least a lower surface of the light emitting element after the first step.

Abstract: A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.

Abstract: Implementations described herein generally relate to methods for depositing etch stop layers, such as AlN layers, using UV assisted CVD. Methods disclosed herein generally include positioning a substrate in a process region of a process chamber; delivering an aluminum-containing precursor to the process region, the aluminum-containing precursor depositing an aluminum species onto the substrate; purging the process region of aluminum-containing precursor using an inert gas; delivering a UV responsive nitrogen-containing precursor to the process region, the UV responsive nitrogen-containing gas being activated using UV radiation to create nitrogen radicals, the nitrogen radicals reacting with the aluminum species to form an AlN layer; and purging the process region of UV responsive nitrogen-containing precursor using an inert gas.

Abstract: A method of manufacturing a photoelectric conversion element including a step of forming a layer containing an organic material and particles dispersed in the organic material on a member including a photoelectric conversion portion and a step of roughening a surface of the layer by dry etching.

Abstract: One method includes forming a conductive feature in a dielectric layer on a substrate. A first hard mask layer and an underlying second hard mask layer are formed on the substrate. The second hard mask layer has a higher etch selectivity to a plasma etch process than the first hard mask layer. The second hard mask layer may protect the dielectric layer during the formation of a masking element. The method continues to include performing plasma etch process to form a trench in the dielectric layer, which may also remove the first hard mask layer. A cap is then formed over the trench to form an air gap structure adjacent the conductive feature.

Abstract: A MEMS device, such as an accelerometer or gyroscope, fabricated in interconnect metallization compatible with a CMOS microelectronic device. In embodiments, a proof mass has a first body region utilizing a thick metal layer that is separated from a thin metal layer. The thick metal layer has a film thickness that is significantly greater than that of the thin metal layer for increased mass. The proof mass further includes a first sensing structure comprising the thin metal layer, but lacking the thick metal layer for small feature sizes and increased capacitive coupling to a surrounding frame that includes a second sensing structure comprising the thin metal layer, but also lacking the thick metal layer. In further embodiments, the frame is released and includes regions with the thick metal layer to better match film stress-induced static deflection of the proof mass.

Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.

Abstract: A plurality of blocking dielectric portions can be formed between a memory stack structure and an alternating stack of first material layers and second material layers by selective deposition of a dielectric material layer. The plurality of blocking dielectric portions can be formed after removal of the second material layers selective to the first material layers by depositing a dielectric material on surfaces of the memory stack structure while avoiding deposition on surfaces of the first material layers. A deposition inhibitor material layer or a deposition promoter material layer can be optionally employed. Alternatively, the plurality of blocking dielectric portions can be formed on surfaces of the second material layers while avoiding deposition on surfaces of the first material layers after formation of the memory opening and prior to formation of the memory stack structure. The plurality of blocking dielectric portions are vertically spaced annular structures.

Abstract: A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers.

Abstract: Ink compositions formulated for inkjet printing the hole injecting layer (HIL) or hole transporting layer (HTL) of an organic light emitting diode (OLED) are provided. The ink compositions contain fluorosurfactants that prevent uncontrolled spreading of the printed ink compositions. Also provided are methods of inkjet printing the HILs or HTLs using the ink compositions.

Abstract: A magnetic junction and method for providing the magnetic junction are described. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The pinned layer has a perpendicular magnetic anisotropy (PMA) energy greater than its out-of-plane demagnetization energy. Providing the pinned layer includes providing a bulk PMA (B-PMA) layer, providing an interfacial PMA (I-PMA) layer on the B-PMA layer and then providing a sacrificial layer that is a sink for a constituent of the first I-PMA layer. An anneal is then performed. The sacrificial layer and part of the first I-PMA layer are removed after the anneal. Additional I-PMA layer(s) are provided after the removing. A remaining part of the first I-PMA layer and the additional I-PMA layer(s) have a thickness of not more than twenty Angstroms.

Abstract: A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.

Abstract: A substrate processing system that includes a substrate processing chamber having one or more sidewalls that at least partially define a substrate processing region and extend away from a bottom wall of the substrate processing chamber at an obtuse angle; a source material holder configured to hold a source material within the substrate processing region; a plasma gun operatively coupled to introduce a plasma beam into the substrate processing region; one or more magnets operatively arranged to generate a magnetic field that guides the plasma beam to the source material holder; and a substrate carrier configured to hold one or more substrates within the substrate processing region.

Abstract: A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.

Abstract: A method for forming a dielectric film in a trench on a substrate by plasma-enhanced atomic layer deposition (PEALD) performs one or more process cycles, each process cycle including: (i) feeding a silicon-containing precursor in a pulse; (ii) supplying a hydrogen-containing reactant gas at a flow rate of more than about 30 sccm but less than about 800 sccm in the absence of nitrogen-containing gas; (iii) supplying a noble gas to the reaction space; and (iv) applying RF power in the presence of the reactant gas and the noble gas and in the absence of any precursor in the reaction space, to form a monolayer constituting a dielectric film on a substrate at a growth rate of less than one atomic layer thickness per cycle.

Abstract: A method of processing a workpiece to create a doped fin structure is disclosed. A portion of the workpiece is subjected to a pre-amorphizing implant to create an amorphized region. This amorphized region is then implanted with dopant species, at an implant energy and dose so that the dopant species are contained within the amorphized region. The doped amorphized region is then subjected to a laser melt anneal which crystallizes the amorphized region. The dopant profile is box-like, and the dopant is confined to the previously amorphized region.

Abstract: A flat panel detector comprises a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element comprises: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor comprises a first electrode and a second electrode. The first electrode comprises an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.