Patents Examined by David Vu
  • Patent number: 10916517
    Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Sheng-Wei Yeh, Yen-Yu Chen, Wen-Hao Cheng, Chih-Wei Lin, Chun-Chih Lin
  • Patent number: 10910292
    Abstract: An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90 and a connection body 50 having a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75. The head part 40 has a second projection protruding 42 toward the electronic element 95 and a first projection 41 protruding from the second projection 42 toward the electronic element 95.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: February 2, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Yuji Morinaga
  • Patent number: 10910321
    Abstract: A semiconductor device includes an interposer disposed on a substrate. A first major surface of the interposer faces the substrate. A system on a chip is disposed on a second major surface of the interposer. The second major surface of the interposer opposes the first major surface of the interposer. A plurality of first passive devices is disposed in the first major surface of the interposer. A plurality of second passive devices is disposed on the second major surface of the interposer. The second passive devices are different devices than the first passive devices.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: February 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chieh Hsieh, Hau Tao, Yung-Tien Kuo
  • Patent number: 10910415
    Abstract: The present disclosure discloses a three-dimensional photodetector and a method of manufacturing the same. The three-dimensional photodetector according to an embodiment of the present disclosure includes a base part formed in the center region of the three-dimensional photodetector; a first bending part formed around the base part; at least one branch part connected to the base part through the first bending part; second bending parts formed on the at least one branch part; bonding parts connected to the at least one branch part through the second bending parts; at least one photoresistor formed on the surface of at least one of the base part and the branch parts; and a stretchable substrate to which the bonding parts are attached, wherein the bonding parts are attached to the stretchable substrate so that the base part has a gap in the thickness direction of the stretchable substrate; and the at least one photoresistor is responsible for tracking the traveling direction of light.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 2, 2021
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jong Hyun Ahn, Won Ho Lee, Yong Jun Lee
  • Patent number: 10903174
    Abstract: An electronic chip includes a substrate made of semiconductor material. Conductive pads are located on a front side of the substrate and cavities extend into the substrate from a back side of the substrate. Each cavity reaches an associated conductive pad. Protrusions are disposed on the back side of the substrate. A conductive layer covers the walls and bottoms of the cavities. The conductive layer includes portions on the back side, each portion partially located on an associated protrusion and electrically connecting two of the conductive pads.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 26, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Sebastien Petitdidier
  • Patent number: 10903198
    Abstract: A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 26, 2021
    Assignee: MEDIATEK INC
    Inventors: Chia-Cheng Chang, I-Hsuan Peng, Tzu-Hung Lin
  • Patent number: 10897024
    Abstract: A light-emitting device includes an anode; a cathode; and an emissive layer disposed between the anode and the cathode, the emissive layer including quantum dots dispersed in a crosslinked matrix formed from one or more crosslinkable charge transport materials. A method of forming the emissive layer of a light-emitting device includes depositing a mixture including quantum dots and one or more crosslinkable charge transport materials on a layer; and subjecting at least a portion of the mixture to UV activation to form an emissive layer including quantum dots dispersed in a crosslinked matrix.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 19, 2021
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Enrico Angioni, James Andrew Robert Palles-Dimmock, Edward Andrew Boardman, Tim Michael Smeeton
  • Patent number: 10892367
    Abstract: A semiconductor device which includes a metal oxide film including a crystal part is provided. A semiconductor device which has a metal oxide film and high field-effect mobility is provided. A highly reliable semiconductor device including a metal oxide film is provided. The semiconductor device includes a first insulator, a first conductor formed over the first insulator, a second insulator formed over the first conductor, an oxide formed over the second insulator, a third insulator formed over the oxide, a second conductor formed over the third insulator, a fourth insulator formed over the third insulator and the second conductor, and a fifth insulator formed over the fourth insulator. The oxide contains In, M (M is Al, Ga, Y, or Sn), and Zn. The oxide includes a first crystal part and a second crystal part. The first crystal part has c-axis alignment. The second crystal part does not have c-axis alignment.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 12, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10892284
    Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. According to embodiments of the present disclosure, the manufacturing method of a display substrate comprises: fabricating a gate electrode, a gate electrode insulating layer, and a semiconductor active layer sequentially on a base substrate; fabricating a first etching stopping layer and a second etching stopping layer on the base substrate with the semiconductor active layer fabricated thereon, wherein the first etching stopping layer is disposed in a display area of the display substrate, the second etching stopping layer is disposed in a peripheral area of the display substrate, and the second etching stopping layer is a non-transparent layer; and fabricating source/drain electrodes by a patterning process, on the base substrate with the first and second etching stopping layers fabricated thereon, wherein the second etching stopping layer is used as an alignment marker in fabricating the source/drain electrodes.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 12, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming Wang, Wei Song, Hui Li
  • Patent number: 10892290
    Abstract: Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder bumps.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: January 12, 2021
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yin Qian, Chia-Chun Miao, Ming Zhang, Dyson H. Tai
  • Patent number: 10892334
    Abstract: An n-type SiC single crystal substrate of the present invention is provided which is a substrate doped with both a donor and an acceptor, and has a difference between a donor concentration and an acceptor concentration in an outer peripheral portion which is smaller than a difference between a donor concentration and an acceptor concentration in a central portion, and is smaller than 3.0×1019/cm3.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: January 12, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Kazuma Eto, Hiromasa Suo, Tomohisa Kato
  • Patent number: 10886171
    Abstract: Integrated circuit (IC) chip “on-die” interconnection features (and methods for their manufacture) may improve signal connections and transmission through a data signal communication channel from one chip, through semiconductor device packaging, and to another component, such as another chip. Such chip interconnection features may include (1) “last silicon metal level (LSML)” data signal “leadway (LDW) routing” traces isolated between LSLM isolation (e.g., power and/or ground) traces to: (2) add a length of the isolated data signal LDW traces to increase a total length of and tune data signal communication channels extending through a package between two communicating chips and (3) create switched buffer (SB) pairs of data signal channels that use the isolated data signal LDW traces to switch the locations of the pairs data signal circuitry and surface contacts for packaging connection bumps.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Kemal Aygun
  • Patent number: 10886305
    Abstract: A display device includes: a substrate; a semiconductor layer of a transistor, on the substrate; a gate electrode of the transistor on the semiconductor layer; and a conductive layer element corresponding to the transistor. The conductive layer element is both electrically connected to a constant voltage source and contacts the substrate.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yunmo Chung, Ilhun Seo, Joosun Yoon, Daewoo Lee, Takyoung Lee
  • Patent number: 10879236
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chiu-Hua Chung, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Tien Sheng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Patent number: 10879298
    Abstract: An image sensor includes: a pixel substrate that includes a plurality of pixels each having a photoelectric conversion unit that generates an electric charge through photoelectric conversion executed on light having entered therein and an output unit that generates a signal based upon the electric charge and outputs the signal; and an arithmetic operation substrate that is laminated on the pixel substrate and includes an operation unit that generates a corrected signal by using a reset signal generated after the electric charge in the output unit is reset and a photoelectric conversion signal generated based upon an electric charge generated in the photoelectric conversion unit and executes an arithmetic operation by using corrected signals each generated in correspondence to one of the pixels.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 29, 2020
    Assignee: NIKON CORPORATION
    Inventor: Shigeru Matsumoto
  • Patent number: 10879253
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 10872846
    Abstract: A solid top terminal for discrete power devices. In one embodiment, an apparatus is formed that includes a first die comprising a transistor, which in turn includes a first electrode such as an emitter. The apparatus also includes a first conductor sintered to an electroplated second conductor such as a solid top terminal. Importantly, the first conductor is electrically coupled to the first electrode.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 22, 2020
    Assignee: Renesas Electronics America Inc.
    Inventor: Jean Claude Harel
  • Patent number: 10867869
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Patent number: 10868199
    Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes a capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: December 15, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10867934
    Abstract: A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Intel IP Corporation
    Inventors: Saravana Maruthamuthu, Thomas Ort, Andreas Wolter, Andreas Augustin, Veronica Sciriha, Bernd Waidhas