Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.

Abstract: A semiconductor device includes a lower insulating layer formed on a primary surface of a semiconductor substrate; a sealing layer formed in contact with a top surface of the lower insulating layer; and a conductive member including a first conductive member formed on the sealing layer and having a first film thickness and a second conductive member formed on the sealing layer in contact with a first conductive member and having a second film thickness that is smaller than the first film thickness.

Abstract: Several aspects of the present technology are directed toward fan-out packaged semiconductor devices having an integrated shield. The shield can include a conductive wall and a conductive cap over a redistribution structure. The shield can surround or at least partially enclose circuits placed or formed on the redistribution structure. The circuits and/or the conductive cap can be covered by an encapsulant, and the conductive cap can be on an upper surface of an encapsulant.

Abstract: A semiconductor device comprising a semiconductor substrate including an upper surface and a lower surface wherein a donor concentration of a drift region is higher than a base doping concentration of the semiconductor substrate, entirely over the drift region in a depth direction connecting the upper surface and the lower surface is provided.

Abstract: A second semiconductor layer is oxidized through a groove and a fourth semiconductor layer is oxidized, a first oxide layer is formed, and a second oxide layer is formed. By oxidizing the entire second semiconductor layer and the fourth semiconductor layer, the first oxide layer and the second oxide layer in an amorphous state are formed.

Abstract: A display panel is provided. The display panel has a display region and a non-display region. The non-display region has an aperture region and a non-aperture region surrounding the aperture region. The display panel includes a plurality of light-emitting elements disposed in the display region. The display panel includes a plurality of first light absorbing patterns and a plurality of second light absorbing patterns disposed in the non-aperture region. The plurality of first light absorbing patterns and the plurality of second light absorbing patterns are configured to absorb different colors of lights.

Abstract: A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.

Abstract: Semiconductor devices having conductive floating gates superimposed on and/or embedded within a conducting channel for managing electromagnetic radiation in the device. The conductive floating gates can comprise a one- or two-dimensional array of asymmetric structures superimposed on and/or embedded within the conducting channel. The conductive floating gates can comprise Nb2N, Ta2N, TaNx, NbNx, WNx, or MoNx or any transition metal nitride compound. The device can include a plurality of conductive floating gates on a rear surface of a barrier layer, wherein each of the conductive floating gates might be separately biased for individual tuning. Antennas for capturing or emitting THz or sub-THz radiation could be attached to the device contacts. Terahertz or infrared radiation could be manipulated by driving a current through the conducting channel into a plasmonic boom regime. Additional manipulation of the electromagnetic radiation could be achieved by having antennas with an appropriate phase angle shift.

Abstract: The embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a substrate, wherein the substrate has a display region and a peripheral region surrounding the display region, the display region has a plurality of pixels arranged in an array, and each of the plurality of pixels includes a light transmission region and a light shielding region, and a light shielding block covering at least a part of the light transmission region of at least one pixel close to the peripheral region of the plurality of pixels.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a first electrode layer formed over a substrate, and a first spacer formed on a sidewall of the first electrode layer. The MIM capacitor structure also includes a first dielectric layer formed on the first spacers, and an end of the first dielectric layer is in direct contact with the first pacer.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: Embodiments include an embedded dynamic random access memory (DRAM) device, a method of forming an embedded DRAM device, and a memory device. An embedded DRAM device includes a dielectric having a logic area and a memory area, and a trace and a via disposed in the logic area of dielectric. The embedded DRAM device further includes ferroelectric capacitors disposed in the memory area of dielectric, where each ferroelectric capacitor includes a first electrode, a ferroelectric layer, and a second electrode, and where the ferroelectric layer surrounds the first electrode of each ferroelectric capacitor and extends along a top surface of the dielectric in the memory area. The embedded DRAM device includes an etch stop layer above the dielectric. The second etch stop in the logic area may have a z-height that is approximately equal to a z-height of a top surface of the second etch stop in the memory area.

Abstract: A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

Abstract: A nonvolatile memory device is provided. The device comprises an active region, a floating gate over the active region and a wordline next to the floating gate. The floating gate has at least two narrow tips adjacent to the wordline and a portion of the floating gate between the narrow tips has a concave profile.

Abstract: A power electronics assembly includes a vapor chamber and a heat-generating device. The vapor chamber includes a housing defining an evaporator side and a condenser side and a pedestal integrally formed with an extending from the evaporator side, the pedestal comprising a non-rectangular shape corresponding to a thermal management objective. The heat-generating device is coupled to the pedestal.

Abstract: The present application relates to a capacitor structure and a method for manufacturing the same, and a memory using the capacitor structure. The method includes the following operations: a substrate is provided; a stacked structure is formed on the substrate, the stacked structure including at least two support material layers arranged at an interval and a sacrificial material layer located between adjacent support material layers; capacitance holes is formed in the stacked structure, each of the capacitance holes including at least three through holes arranged in isolation; a lower electrode is formed, the lower electrode at least covering a side wall and a bottom of each through hole; the sacrificial material layer is removed, and a capacitance dielectric layer is formed on a surface of the lower electrode; and an upper electrode is formed on a surface of the capacitance dielectric layer.

Abstract: In an embodiment, a first recess and a second recess, designed to reach a first semiconductor layer, are formed in the portions of a first threading dislocation and a second threading dislocation having reached the surface. Further, the first semiconductor layer is oxidized through the first recess and the second recess to form an insulating film configured to cover the lower surface of a second semiconductor layer.

Abstract: As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

Abstract: A display device includes an organic emission layer in which a first pixel area, a second pixel area and a third pixel area are defined, a color filter layer disposed on the organic emission layer and including first to third color filters overlapping the first to third pixel areas, respectively, where the first to third color filters emit first light to third light, respectively, a first optical filter layer disposed on the color filter layer and which transmits at least one of the first light and the second light and reflects or absorbs the third light, and a light-focusing layer disposed between the color filter layer and the organic emission layer and including first to third light-focusing parts overlapping the first to third pixel areas, respectively, where at least one of the first to third color filters includes quantum dots.

Abstract: A photoelectric device includes a first photoelectric conversion layer including a heterojunction that includes a first p-type semiconductor and a first n-type semiconductor, a second photoelectric conversion layer on the first photoelectric conversion layer and including a heterojunction that includes a second p-type semiconductor and a second n-type semiconductor. A peak absorption wavelength (?max1) of the first photoelectric conversion layer and a peak absorption wavelength (?max2) of the second photoelectric conversion layer are included in a common wavelength spectrum of light that is one wavelength spectrum of light of a red wavelength spectrum of light, a green wavelength spectrum of light, a blue wavelength spectrum of light, a near infrared wavelength spectrum of light, or an ultraviolet wavelength spectrum of light, and a light-absorption full width at half maximum (FWHM) of the second photoelectric conversion layer is narrower than an FWHM of the first photoelectric conversion layer.