Patents Examined by David Z Chen
  • Patent number: 7977724
    Abstract: A capacitor includes a cylindrical storage electrode formed on a substrate. A ring-shaped stabilizing member encloses an upper portion of the storage electrode to structurally support the storage electrode and an adjacent storage electrode. The ring-shaped stabilizing member is substantially perpendicular to the storage electrode and extends in a direction where the adjacent storage electrode is arranged. A dielectric layer is formed on the storage electrode. A plate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Je-Min Park
  • Patent number: 7977662
    Abstract: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: July 12, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-Chang Ryoo, Jong-Woo Ko, Yoon-Jong Song
  • Patent number: 7968929
    Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Anil K. Chinthakindi, Eric Thompson
  • Patent number: 7968940
    Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: June 28, 2011
    Assignee: Anpec Electronics Corporation
    Inventor: Florin Udrea
  • Patent number: 7964910
    Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventor: Thomas W. Dyer
  • Patent number: 7964917
    Abstract: A semiconductor device includes a plurality of first MIS transistors and a plurality of second MIS transistors formed on a semiconductor substrate and a liner insulating film applying stress along the gate length direction. Each of the first MIS transistors includes first L-shaped sidewalls each having an L-shaped cross-sectional shape, and each of the second MIS transistors includes second L-shaped sidewalls each having an L-shaped cross-sectional shape and outer sidewalls. The minimum thickness of a part of the liner insulating film located on each of second source/drain regions of the second MIS transistor is larger than the minimum thickness of a part thereof located on each of first source/drain regions of the first MIS transistor.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventor: Susumu Akamatsu
  • Patent number: 7936056
    Abstract: An airtight sealed package with a device sealed therein in an airtight manner under vacuum, the device being placed in a space defined in the airtight sealed package by a lid and a substrate, includes at least one pressure adjustment unit provided on at least one of the lid and the substrate, and configured to receive energy from an outside of the airtight sealed package, with the device sealed in the airtight manner in the airtight sealed package, to adjust pressure in the space. An energy transmission member transmits the energy to the pressure adjustment unit.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: May 3, 2011
    Assignee: Olympus Corporation
    Inventor: Tomoyuki Hatakeyama
  • Patent number: 7932551
    Abstract: A nonvolatile memory device is provided. In the nonvolatile memory device, a semiconductor substrate of a first conductivity type includes first and second fins. A common bit line electrode connects one end of the first fin to one end of the second fin. Control gate electrodes cover the first and second fins and expand across the top surface of each of the first and second fins. A first string selection gate electrode positioned between the common bit line electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins. A second string selection gate electrode positioned between the first string selection gate electrode and the control gate electrodes may cover the first and second fins and expand across the top surface of each of the first and second fins.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-joo Kim, Yoon-dong Park, June-mo Koo, Suk-pil Kim, Sung-jae Byun
  • Patent number: 7902663
    Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: March 8, 2011
    Assignee: Powertech Technology Inc.
    Inventor: Wen-Jeng Fan
  • Patent number: 7902021
    Abstract: A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate (203), (b) first and second gate electrodes (219) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first (223) and second (225) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist (231) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: March 8, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Anadi Srivastava
  • Patent number: 7888808
    Abstract: A system in package integrating a plurality of semiconductor chips, including a first chip mounted commonly in a plurality of system in packages and at least including a CPU, a second chip having a different specification for each of the plurality of system in packages depending on a connection of internal lines, and a module substrate including the first chip and the second chip adjacent to each other and having a shape common to the plurality of system in packages. The first chip includes a first module connection terminal on the first chip along a first side facing the second chip or in an area different from the first chip and facing the second chip. A second side of the second chip includes a second module connection terminal to be connected with the first chip. The first and the second module connection terminals are connected by a bonding wire.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Katsunobu Suzuki, Junichi Iwasaki
  • Patent number: 7872297
    Abstract: The present invention relates to a flash memory device and its fabrication method. The device comprises a structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device. A new device structure according to the present invention is based on a recessed channel capable of implementing highly-integrated/high-performance and 2-bit/cell. The proposed device suppresses the short channel effect, reduces the cell area, and enables 2-bit/cell by forming the charge storage node as a spacer inside the recessed channel. Moreover, if selectively removing the dielectric films around the recessed silicon surface, the sides as well as the surface of the recessed channel is exposed. A spacer can be used as a storage node, thereby improving the channel controllability of the control electrode and the on-off characteristic of a device. The proposed structure also resolves the threshold voltage problem and improves the write/erase speeds.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: January 18, 2011
    Assignee: SNU R&DB Foundation
    Inventor: Jong-Ho Lee
  • Patent number: 7859080
    Abstract: The invention provides an electronic component which has an improved breakdown limit value of withstand voltage and improved insulation properties and which can be made compact and provided with a multiplicity of layers and a great capacity. The electronic component includes a first conductor having a bottom conductor formed on a substrate and a raised conductor formed to protrude from the bottom conductor, a dielectric film formed on the raised conductor, and a second conductor formed on the dielectric film to constitute a capacitor element in combination with the raised conductor and the dielectric film.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: December 28, 2010
    Assignee: TDK Corporation
    Inventors: Hajime Kuwajima, Akira Furuya, Masahiro Miyazaki, Makoto Shibata
  • Patent number: 7846826
    Abstract: A gate dielectric film, a poly-silicon film, a film of a refractory metal such as tungsten, and a gate cap dielectric film are sequentially laminated on a semiconductor substrate. The gate cap dielectric film and the refractory metal film are selectively removed by etching. Thereafter, a double protection film including a silicon nitride film and a silicon oxide film is formed on side surfaces of the gate cap dielectric film, the refractory metal film, and the poly-silicon film. The poly-silicon film is etched using the double protection film as a mask. Thereafter, the semiconductor substrate is light oxidized to form a silicon oxide film on side surfaces of the poly-silicon film. Accordingly, a junction leakage of a MOSFET having a gate electrode of a poly-metal structure, particularly, a memory cell transistor of a DRAM, can be further reduced.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: December 7, 2010
    Assignee: Elpida Memory Inc.
    Inventors: Kiyonori Oyu, Kensuke Okonogi
  • Patent number: 7847335
    Abstract: A non-volatile semiconductor memory device includes a gate stack formed on a substrate, semiconductor spacers, an oxide-nitride-oxide stack, and a contact pad. The semiconductor spacers are adjacent to sides of the gate stack and over the substrate. The oxide-nitride-oxide stack is located between the spacers and the gate stack, and located between the spacers and the substrate, such that the oxide-nitride-oxide stack has a generally L-shaped cross-section on at least one side of the gate stack. The contact pad is over and in electrical contact with the gate electrode and the semiconductor spacers. The contact pad may be further formed into recessed portions of the oxide-nitride-oxide stack between the gate electrode and the semiconductor spacers. The contact pad may include an epitaxial silicon having a metal silicide formed thereon.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: December 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzyh-Cheang Lee, Tsung-Lin Lee, Jiunn-Ren Hwang
  • Patent number: 7838966
    Abstract: A semiconductor device may include a resistance pattern including a resistance material on a substrate. The resistance pattern may include first and second spaced apart base elements, a bridge element, and first, second, third, and fourth extension elements. The first and second base elements may be substantially parallel, and the bridge element may be connected between respective center portions of the first and second spaced apart base elements. The first and second extension elements may be connected to opposite ends of the first base element and may extend toward the second base element, and the third and fourth extension elements may be connected to opposite ends of the second base element and may extend toward the first base element. Related methods are also discussed.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: November 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiao Quan Wang, Chang-Bong Oh, Seung-Hwan Lee
  • Patent number: 7821072
    Abstract: In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type SRAM region NS are covered with a layered film including a tensile stress applying film and a compressive stress applying film.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventor: Naoki Kotani
  • Patent number: 7812415
    Abstract: A semiconductor device including a gate insulating layer formed over a semiconductor substrate; a gate insulating layer pattern formed over an exposed uppermost surface of the semiconductor substrate along the same horizontal plane as the gate insulating layer; an isolation insulating layer formed over the gate insulating layer; a plurality of first gate conductive patterns formed over the gate insulating layer and the gate insulating layer pattern; a source/drain conductor formed over an exposed uppermost surface of the semiconductor substrate; a second gate conductive pattern formed over one of the plurality of the first gate conductive patterns that is provided over the gate insulating layer pattern; a plurality of salicide layers formed over the second gate conductive pattern, the source/drain conductor, and at least one of the plurality of first gate conductive patterns that are provided over the gate insulating layer; and a pair of spacers formed over the gate insulating layer pattern and on sidewalls o
    Type: Grant
    Filed: November 23, 2007
    Date of Patent: October 12, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong-Ho Park
  • Patent number: 7763500
    Abstract: First, a base structure provided with the main parts of a memory cell is prepared, and a lower electrode comprising a polycrystalline silicon film is thereafter formed on the base structure. Next, the surface of the lower electrode is thermally nitrided at a predetermined temperature to form a silicon nitride film. In the thermal nitridation of the lower electrode, the temperature is increased to a predetermined nitriding temperature, after which the temperature is reduced at a rate that is more gradual than usual. Aluminum oxide (Al2O3) or another metal oxide dielectric film is thereafter formed as the capacitive insulating film on the lower electrode, and an upper electrode is formed on the capacitive insulating film.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: July 27, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Takashi Arao, Kenichi Koyanagi, Kenji Komeda, Naruhiko Nakanishi, Hideki Gomi
  • Patent number: 7745941
    Abstract: A first semiconductor chip and a second semiconductor chip which form a stack are mounted on a module substrate by deflecting a center position of the semiconductor chips from the module substrate. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is shorter, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are directly connected with a wire. In the side where the distance from the edge of the deflected semiconductor chip to the edge of a module substrate is longer, the electrode pad on the first semiconductor chip and the electrode pad on the second semiconductor chip are combined with the corresponding bonding lead on the module substrate with a wire.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: June 29, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kuroda, Katsuhiko Hashizume