Patents Examined by David Ziskind
  • Patent number: 8154005
    Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: April 10, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Kang-Jay Hsia, Christopher J. Petti, Calvin K. Li
  • Patent number: 8143690
    Abstract: Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: March 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-kyu Park, Byung-sun Kim, Tae-jung Lee, Kee-in Bang
  • Patent number: 8134137
    Abstract: Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8133754
    Abstract: An image sensor is disclosed that includes a first substrate including an electric junction region, a transistor, and a metal line connected to the electric junction region or the transistor; and a photodiode formed on the first substrate. The first substrate is formed at an upper portion thereof with a reflective layer to reflect light back to the photodiode.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: March 13, 2012
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Seoung Hyun Kim
  • Patent number: 8119509
    Abstract: A semiconductor device comprises a plurality of vertical transistors each comprising barrier metal layers corresponding to source/drain regions in which a conduction region is formed under a channel region having a pillar form, and a bit line comprising a metal layer to connect the plurality of vertical transistors.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: February 21, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Young Man Cho
  • Patent number: 8110483
    Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Lilian Kamal, legal representative, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Jr., Robert R. Robison, William R. Tonti
  • Patent number: 8110927
    Abstract: A power module having at least one electric power component, such as a power electronic semiconductor component. An electrical contact for a load current is formed on a lower surface and also on an upper surface of the power semiconductor component. To reduce an explosion pressure and accept power when the power electronic semiconductor component is overloaded, a hollow space filled with at least one electrically conducting particle is formed on an electrical contact surface of the electrical contact. In case of a short circuit, an arc is initially generated above the semiconductor element thickness of the power semiconductor component, whereupon the filling in the hollow space takes over current conduction. Preferably, the filling in the hollow space is a plurality of spherical electrically conducting particles. The explosion pressure can escape into interstices in the filling if there is a short circuit. Furthermore, metal vapors are cooled and are condensed.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: February 7, 2012
    Assignee: Siemens Aktiengesellschaft
    Inventor: Herbert Schwarzbauer
  • Patent number: 8110831
    Abstract: A display device is provided with a pair of a first electrode and a second electrode at least one of which is transparent or translucent and a phosphor layer formed so as to be sandwiched between the first electrode and the second electrode, and the phosphor layer has a polycrystal structure made of a first semiconductor substance in which a second semiconductor substance different from the first semiconductor substance is segregated on a grain boundary of the polycrystal structure, and the phosphor layer has a plurality of pixel regions that are selectively allowed to emit light in a predetermined range thereof and non-pixel regions that divide at least one portion of the pixel regions.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: February 7, 2012
    Assignee: Panasonic Corporation
    Inventors: Masayuki Ono, Shogo Nasu, Toshiyuki Aoyama, Eiichi Satoh, Reiko Taniguchi, Masaru Odagiri
  • Patent number: 8093599
    Abstract: A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: January 10, 2012
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida
  • Patent number: 8076668
    Abstract: An atomic scale electroconductivity device with electrostatic regulation is provided that includes a perturbing species having a localized electronic charge ol a dangling bond. A sensing species having an electronic conductivity is placed in proximity to the perturbing species at a distance sufficient to induce a change in the electronic conductivity associated with the localized electronic charge. Electronics are provided to measure the conductivity via the sensing species. The dangling bond functions as a single atom gate electrode.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: December 13, 2011
    Assignees: The Governers of the University of Alberta, National Research Council of Canada
    Inventors: Robert A. Wolkow, Paul G. Piva, Jason L. Pitters, Gino A. Dilabio
  • Patent number: 8058660
    Abstract: Disclosed herein is a semiconductor light emitting device including: (A) an underlying layer configured to be formed on a major surface of a substrate having a {100} plane as the major surface; (B) a light emitting part; and (C) a current block layer, wherein the underlying layer is composed of a III-V compound semiconductor and is formed on the major surface of the substrate by epitaxial growth, the underlying layer extends in parallel to a <110> direction of the substrate, a sectional shape of the underlying layer obtained when the underlying layer is cut along a virtual plane perpendicular to the <110> direction of the substrate is a trapezoid, and oblique surfaces of the underlying layer corresponding to two oblique sides of the trapezoid are {111}B planes, and the top surface of the underlying layer corresponding to an upper side of the trapezoid is a {100} plane.
    Type: Grant
    Filed: September 11, 2008
    Date of Patent: November 15, 2011
    Assignee: Sony Corporation
    Inventors: Sachio Karino, Eiji Takase, Makoto Oogane, Tsuyoshi Nagatake, Michiru Kamada, Hironobu Narui, Nobukata Okano
  • Patent number: 8039965
    Abstract: A semiconductor device with a reduced layout area includes pads disposed between a first voltage line and a second voltage line; first and second driver units adjacently disposed at an upper portion or a lower portion of the respective pads; and a metal line disposed between the pads and supplying power commonly to the first and second driver units.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: October 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyun Seung Choi
  • Patent number: 8017468
    Abstract: A method of manufacturing a semiconductor device in which the formation of buried wiring is facilitated includes: forming columnar patterns, which are arranged in a two-dimensional array, and bridge patterns, which connect the columnar patterns in a column direction, on a main surface of a silicon substrate; injecting an impurity in a surface portion of each of the columnar patterns and bridge patterns and in surface portions of the silicon substrate, thereby forming impurity injection layers; forming a side wall on sides of the columnar patterns and bridge patterns; removing the impurity injection layer, which has been formed in the silicon substrate, with the exception of the impurity injection layer covered by the bottom portions of the side walls; removing the side walls by etch-back; and thermally oxidizing the surface portion of the bridge patterns and then etching away the same. Buried wiring extending in the column direction of the columnar patterns is formed within the silicon substrate.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: September 13, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroyuki Fujimoto
  • Patent number: 7932154
    Abstract: In a non-volatile flash memory device, and a method of fabricating the same, the device includes a semiconductor substrate, a source region and a drain region disposed in the semiconductor substrate to be spaced apart from each other, a tunneling layer pattern, a charge trap layer pattern and a shielding layer pattern, which are sequentially stacked on the semiconductor substrate between the source region and the drain region, adjacent to the source region, a first channel region disposed in the semiconductor substrate below the tunneling layer pattern, a gate insulating layer disposed on the semiconductor substrate between the drain region and the first channel region, a second channel region disposed in the semiconductor substrate below the gate insulating layer, a concentration of the second channel region being different from that of the first channel region, and a gate electrode covering the shielding layer pattern and the gate insulating layer.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Su Kim, Sung-Taeg Kang, In-Wook Cho, Jeong-Hwan Yang