Patents Examined by Davienne Monbleau
  • Patent number: 10266950
    Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Inventors: Mona M. Eissa, Yousong Zhang, Mark Jenson
  • Patent number: 10262947
    Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba, Piyush Savalia
  • Patent number: 10199300
    Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: February 5, 2019
    Inventor: Yoshiaki Goto
  • Patent number: 10192892
    Abstract: A device includes a backplane having multiple output terminals arranged in an array on an output surface of the backplane. The device further includes an active matrix array comprising thin film solid state optical switches coupled respectively between an input terminal of the backplane and the output terminals. Storage capacitors may be coupled respectively to the output terminals. A pixelated light source provides pixelated light that controls the optical switches.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 29, 2019
    Assignee: Palo Alto Research Center Incorporated
    Inventors: JengPing Lu, David K. Biegelsen, Patrick Yasuo Maeda
  • Patent number: 10141408
    Abstract: A method and an arrangement for reducing a contact resistance of a two-dimensional crystal material are provided. An example method may include forming a contact material layer on a two-dimensional crystal material layer; performing ion implantation; and performing thermal annealing.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 27, 2018
    Inventors: Kunpeng Jia, Yajuan Su, Huilong Zhu, Chao Zhao
  • Patent number: 10141478
    Abstract: A light emitting device including a substrate, a first conductive layer on the substrate, a second conductive layer on the first conductive layer, a metal layer on the second conductive layer, a light emitting structure on the metal layer and the second conductive layer, the light emitting structure including a first semiconductor layer containing AlGaN, an active layer, and a second semiconductor layer containing AlGaN, a first electrode on the light emitting structure, and a passivation layer disposed on a side surface of the light emitting structure.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: November 27, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Hwan Hee Jeong, Kwang Ki Choi, June O Song, Sang Youl Lee
  • Patent number: 10134631
    Abstract: A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 10134759
    Abstract: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: November 20, 2018
    Inventors: Nicolas Loubet, James Kuss
  • Patent number: 10128414
    Abstract: A chip substrate includes: a plurality of conductive layers horizontally stacked and constituting the chip substrate; a plurality of insulation layers alternately with the conductive layers and electrically separating the conductive layers; a lens insert comprising a groove having a predetermined number of edges on the upper surface of the chip substrate and having a cross-section wherein an arc is formed at the region where the extended edges meet; a cavity comprising a groove reaching down to a predetermined depth towards the area accommodating the insulation layer within the internal region of the lens insert; and a plurality of joining grooves formed on the surface of the lens insert. Thus, the lens to be inserted also can be formed to be a shape comprising straight lines so that the manufacturing process of the lens to be inserted into the chip substrate can be further simplified.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 13, 2018
    Assignee: Point Engineering Co., Ltd.
    Inventors: Seung Ho Park, Tae Hwan Song
  • Patent number: 10090287
    Abstract: A deep trench capacitor having a high capacity is formed into a deep trench having faceted sidewall surfaces. The deep trench is located in a bulk silicon substrate that contains an upper region of undoped silicon and a lower region of n-doped silicon. The lower region of the bulk silicon substrate includes alternating regions of n-doped silicon that have a first boron concentration (i.e., boron deficient regions), and regions of n-doped silicon that have a second boron concentration which is greater than the first boron concentration (i.e., boron rich regions).
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Keith E. Fogel, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10072291
    Abstract: The present invention is a biosensor apparatus that includes a substrate, a source on one side of the substrate, a drain spaced from the source, a conducting channel between the source and the drain, an insulator region, and receptors on a gate region for receiving target material. The receptors are contacted for changing current flow between the source and the drain. The source and the drain are relatively wide compared to length between the source and the drain through the conducting channel.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: September 11, 2018
    Inventor: James Holm-Kennedy
  • Patent number: 10053971
    Abstract: A method for detecting stick-slip in a drillstring includes (a) measuring a parameter that is a function of a torque applied to the drillstring by a top drive system over a selected time period, the measuring being performed by at least one surface sensor that produces measurement data including torque values over a frequency range; (b) filtering out measurement data that has a frequency outside a selected frequency band, the selected frequency band including a resonant frequency of the drillstring; (c) identifying a minimum and a maximum torque value in the filtered measurement data and determining a difference of these two values; (d) determining a surface stick-slip index by dividing the difference of the maximum and minimum torque values by an average torque value over the selected time period; and (e) displaying the surface stick-slip index on a display.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 21, 2018
    Assignee: Pason Systems Corp.
    Inventors: Stephen William Lai, Christopher Darren Salvador, Kenneth Charles Horovatin, Timothy Keith Walter
  • Patent number: 10056464
    Abstract: Embodiments of the invention provide methods for forming III-V gate-all-around field effect transistors on silicon substrates that utilize Aspect-Ratio Trapping to reduce or eliminate dislocation defects associated with lattice mismatches. A field dielectric material defining a trench is formed on a crystalline silicon substrate. A channel feature comprising III-V material is subsequently formed inside the trench. Source/drain features are then formed at both ends of the channel feature inside the trench. Lastly, gate dielectric layers and a gate feature are formed surrounding a portion of the channel feature.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: August 21, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Sanghoon Lee
  • Patent number: 10050053
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a multilayer body provided on the substrate. The multilayer body has electrode films and insulating films. The electrode films contain silicon, the insulating films contain silicon oxide. Each of the electrode films and each of the insulating films are alternately stacked. A hole is formed in the multilayer body, and the hole vertically extends in the multilayer body. The electrode films include a first electrode film and a second electrode film located below the first electrode film. Carbon concentration of the first electrode film is higher than carbon concentration of the second electrode film.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: August 14, 2018
    Inventor: Merii Inaba
  • Patent number: 10050150
    Abstract: A thin-film transistor includes: an oxide semiconductor layer having a channel region, a source region, and a drain region; a gate insulating layer disposed above the oxide semiconductor layer; a gate electrode disposed at a position that is above the gate insulating layer and opposing the channel region; and a metal oxide layer stacked on the oxide semiconductor layer and in contact with the source region and the drain region. The metal oxide layer includes, as a main component, an oxide of a second metal whose bond dissociation energy with oxygen is greater than that of a first metal included in the oxide semiconductor layer. A first concentration ratio of oxygen to the second metal in an interface layer between the metal oxide layer and the oxide semiconductor layer is greater than a second concentration ratio of the same in a bulk layer of the metal oxide layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: August 14, 2018
    Assignee: JOLED INC.
    Inventors: Emi Kobayashi, Arinobu Kanegae, Yusuke Fukui
  • Patent number: 10050173
    Abstract: A light emitting device includes a semiconductor light emitting unit and a light-transmitting substrate. The light-transmitting substrate includes an upper surface having two long sides and two short sides and a side surface, and the semiconductor light emitting unit is disposed on the upper surface. The side surface includes two first surfaces, two second surfaces, and rough micro-structures. Each of the first surfaces is connected to one of the long sides of the upper surface, and each of the second surfaces is connected to one of the short sides of the upper surface. The rough micro-structures are formed on the first surfaces and the second surfaces, a covering rate of the rough micro-structures on each of the first surfaces is greater than or equal to a covering rate of the rough micro-structures on each of the second surfaces. A manufacturing method of the light emitting device is also provided.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: August 14, 2018
    Assignee: Genesis Photonics Inc.
    Inventors: Jing-En Huang, Kai-Shun Kang, Yu-Chen Kuo, Fei-Lung Lu, Teng-Hsien Lai
  • Patent number: 10042922
    Abstract: A chatter database system, which includes a central chatter database, which is fed with data corresponding to the machining and chatter conditions of machining tools, particularly a milling, turning, drilling or boring machine. The data fed to the central chatter database is obtained and collected from at least two individual machining tools included in the chatter database system. The data is sent to the central chatter database via a data connection, preferably via a secured network, to generate chatter stability maps based on real encountered conditions.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: August 7, 2018
    Assignee: Mikron Agie Charmilles AG
    Inventors: Jean-Philippe Besuchet, Jérémie Monnin
  • Patent number: 10038039
    Abstract: An organic light emitting diode display device includes a substrate including a display region, wherein a plurality of pixel regions are defined in the display region; a first electrode over the substrate and in each of the plurality of pixel regions; a bank including a lower layer and an upper layer on the first electrode, the lower layer disposed on edges of the first electrode and having a first width and a first thickness, the upper layer disposed on the lower layer and having a second width smaller than the first width; an organic emitting layer on the first electrode and a portion of the lower layer; and a second electrode on the organic emitting layer and covering an entire surface of the display region.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 31, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Dae-Jung Choi, Jae-Ki Lee, Ki-Soub Yang, Hwang-Un Seo, Hong-Myeong Jeon, Seung-Ryul Choi, A-Ryoung Lee, Han-Hee Kim, Geum-Young Lee, Kang-Hyun Kim
  • Patent number: 10020287
    Abstract: Pass-through interconnect structures for microelectronic dies and associated systems and methods are disclosed herein. In one embodiment, a microelectronic die assembly includes a support substrate, a first microelectronic die positioned at least partially over the support substrate, and a second microelectronic die positioned at least partially over the first die. The first die includes a semiconductor substrate, a conductive trace extending over a portion of the semiconductor substrate, a substrate pad between the trace and the portion of the semiconductor substrate, and a through-silicon via (TSV) extending through the trace, the substrate pad, and the portion of the semiconductor substrate. The second die is electrically coupled to the support substrate via a conductive path that includes the TSV.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 10, 2018
    Assignee: Micron Technology, Inc.
    Inventors: David S. Pratt, Kyle K. Kirby, Dewali Ray
  • Patent number: 10020269
    Abstract: Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 10, 2018
    Assignee: Skyworks Solutions. Inc.
    Inventors: Kim Rene Smith, Paul T. DiCarlo, Michael David Hill