Abstract: In an embodiment, this invention discloses a top-drain lateral diffusion metal oxide field effect semiconductor (TD-LDMOS) device supported on a semiconductor substrate. The TD-LDMOS includes a source electrode disposed on a bottom surface of the semiconductor substrate. The TD-LDMOS further includes a source region and a drain region disposed on two opposite sides of a planar gate disposed on a top surface of the semiconductor substrate wherein the source region is encompassed in a body region constituting a drift region as a lateral current channel between the source region and drain region under the planar gate. The TD-LDMOS further includes at least a trench filled with a conductive material and extending vertically from the body region near the top surface downwardly to electrically contact the source electrode disposed on the bottom surface of the semiconductor substrate.

Abstract: The present application discloses an array substrate comprising a base substrate, a row of a plurality of pixel units, and a first gate line and a first common electrode line adjacent to the row of the plurality of pixel units and on a first side of the row of the plurality of pixel units in plan view of the array substrate. The first gate line and the first common electrode line are spaced apart by a gap; and a light shield at least partially covering the gap for reducing light leakage from the gap.

Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

Abstract: An image sensor including a semiconductor layer. A light absorber layer couples with the semiconductor layer at a pixel of the image sensor and absorbs incident light to substantially prevent the incident light from entering the semiconductor layer. The light absorber layer heats a depletion region of the semiconductor layer in response to absorbing the incident light, creating electron/hole pairs. The light absorber layer may include one or more narrow bandgap materials.

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract: A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract: Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.

Abstract: A method includes isolating a first and at least a second region on a semiconductor substrate, and forming one or more devices on each of the first and at least second regions. Forming the one or more devices includes forming at least one gate structures in each of the first and at least second regions on a first surface of the substrate, depositing a spacer over the gate structures in each of the first and the at least second regions and over the first surface of the substrate, etching horizontal portions of the spacer in the first region, growing epitaxial portions in the first region in alignment with said at least one gate structure in the first region, oxidizing exposed surfaces of the epitaxial portions in the first region, and repeating the etching, growing and oxidizing steps for the at least second region.

Abstract: The invention relates to an optoelectronic device comprising microwires or nanowires, each having at least one active portion (34, 39) between two insulated portions (32, 36, 40), the active portion having inclined flanks or having a diameter different from the diameter of at least one of the two insulated portions.

Abstract: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.

Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

Abstract: A flexible display panel and a manufacturing method which is capable of removing a non-display area without damaging a display element layer, the flexible display panel includes a flexible substrate which includes a display area and a peripheral area outside of the display area, a display element layer disposed on the flexible substrate, and a neutral plane balancing layer disposed on the display element layer in the peripheral area, wherein the peripheral area of the flexible substrate in which the neutral plane balancing layer is disposed is folded towards a rear side of the display area along a first bending line, and the neutral plane balancing layer overlaps the first bending line.

Abstract: A semiconductor device includes a layered structure forming multiple carrier channels including at least one n-type channel formed in a first layer made of a first material and at least one p-type channel formed in a second layer made of a second material and a set of electrodes for providing and controlling carrier charge in the carrier channels. The first material is different than the second material, and the first and the second materials are selected such that the n-type channel and the p-type channel have comparable switching frequency and current capability.

Abstract: One illustrative method disclosed herein includes performing a first plurality of epitaxial deposition processes to form a first plurality of semiconductor materials selectively above the N-active region while masking the P-active region, performing a second plurality of epitaxial deposition processes to form a second plurality of semiconductor materials selectively above the P-active region while masking the N-active region, forming an N-type transistor in and above the N-active region and forming a P-type transistor in and above the P-active region.

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

Abstract: A compliant electrostatic transfer head and method of forming a compliant electrostatic transfer head are described. In an embodiment, a compliant electrostatic transfer head includes a base substrate, a cavity template layer on the base substrate, a first confinement layer between the base substrate and the cavity template layer, and a patterned device layer on the cavity template layer. The patterned device layer includes an electrode that is deflectable toward a cavity in the cavity template layer. In an embodiment, a second confinement layer is between the cavity template layer and the patterned device layer.

Abstract: A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with fewer defects such as grain boundaries is provided. One embodiment of the present invention is a semiconductor device including an oxide semiconductor, an insulator, and a conductor. The oxide semiconductor includes a region overlapping with the conductor with the insulator therebetween. The oxide semiconductor includes a crystal grain with an equivalent circle diameter of 1 nm or more and a crystal grain with an equivalent circle diameter less than 1 nm.

Abstract: One illustrative method of forming a TFET device includes forming a first semiconductor material that extends for a full length of a drain region, a gate region and a source region of the device, masking the drain region while exposing at least a portion of the gate region and exposing the source region, forming a second semiconductor material above the gate region and above the source region, forming a third semiconductor material above the second semiconductor material and above the gate region and above the source region, the third semiconductor material being doped with an opposite type of dopant material than in the first semiconductor material, masking the drain region, and forming a gate structure above at least a portion of the exposed gate region.