Abstract: A system for chassis management includes a plurality of motherboards of a chassis, a plurality of baseboard management controllers (BMCs), and at least one chassis level component. Each of the plurality of BMCs is associated with one of the plurality of motherboards. The plurality of BMCs are interconnected via a first communication bus. The plurality of BMCs and the at least one chassis level component are interconnected via a second communication bus. One BMC of the plurality of BMCs is configured to operate as a virtual chassis management controller (VCMC) for the chassis. The VCMC is configured to exchange data with other BMCs of the plurality of BMCs over the first communication bus and manage the at least one chassis level component over the second communication bus.

Abstract: A processor includes a core and an interrupt controller. The interrupt controller includes logic to read interrupt data from a memory, the interrupt data including a timestamp, an allowable delay value, and at least one interrupt vector. The interrupt controller also includes a delay-comparison circuit to determine a time lapse based on the timestamp and a system clock signal and to compare the time lapse to the allowable delay value. Further, the interrupt controller includes a second logic to determine whether to invoke an interrupt handler based on the comparison of the time lapse to the allowable delay value.

Abstract: Dynamically bypassing a peripheral component interconnect (PCI) switch including preparing, during run time, a PCI host bridge for disconnection from the PCI switch, wherein the PCI host bridge is connected to a first PCI slot via the PCI switch; toggling, during run time, an electrical switch, wherein toggling the electrical switch bypasses the PCI switch and creates a direct connection between the PCI host bridge and the first PCI slot; and configuring, during run time, the PCI host bridge for the direct connection between the PCI host bridge and the first PCI slot.

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Abstract: A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic.

Abstract: A control device and corresponding motor vehicle for connecting a CAN bus to a radio network, having the following features: the control device includes a wireless controller, a microcontroller, a first CAN transceiver and a second CAN transceiver; the microcontroller is connected, on the one hand, to the wireless controller and, on the other hand, to the CAN transceivers; the first CAN transceiver is connected to the second CAN transceiver; the first CAN transceiver is configured in such a manner that it suppresses transmission via the CAN bus and supports reception via the CAN bus in a normal mode and supports transmission and reception in a diagnostic mode; and the second CAN transceiver is configured in such a manner that it changes the first CAN transceiver from the normal mode to the diagnostic mode when the second CAN transceiver receives a wake-up frame via the CAN bus.

Abstract: A method and apparatus of performing a data transmission from an electronic device or a peripheral device of an electronic device to a peripheral device of a remote electronic device is disclosed. One example method of performing the data transmission may include transmitting data designated for the remote peripheral device to a local virtual device object. The data that is received by the local virtual device object is transmitted via at least one communication interface or peripheral device of the electronic device to at least one remote communication interface or peripheral device of the remote electronic device. The data arriving at the least one remote communication interface or peripheral device of the remote electronic device is received by a remote virtual device object and transmitted to the designated remote peripheral device.

Abstract: A universal serial bus circuit including a power circuit and a terminating circuit is provided. The power circuit provides a differential signal. The terminating circuit is coupled to the power circuit. The terminating circuit receives the differential signal through the first signal output terminal and the second signal output terminal, and the terminating circuit includes a first load circuit and a second load circuit. When the universal serial bus circuit is operated in a handshake mode, the terminating circuit receives the differential signal through the first load circuit and the second load circuit, and outputs a pulse signal through the first signal output terminal and the second signal output terminal. When the universal serial bus circuit is operated in a normal mode, the terminating circuit receives the differential signal through the first load circuit, and outputs a data signal through the first signal output terminal and the second signal output terminal.

Abstract: The present disclosure provides a server system including a rack, a rack management controller, host devices, storage devices and two signal switches. The rack management controller generates a controlling signal. The host devices are located in the rack. The storage devices are electrically connected to the host devices respectively, are disposed in the rack and located under the host devices. The two signal switches are electrically connected to the host devices and the rack management controller respectively, each of the signal switches is electrically connected to the storage devices, and the two signal switches are disposed in the rack and located above the host devices. Each of the host devices receives the control signal through the two signal switches, so as to match one of the storage devices, such that each of the host devices performs the access and process operation for the data of the matched storage device thereof.

Abstract: A system includes a slave device, and first and second master devices. A chipset of the slave device is capable of communication with a specific number of master devices. The first master device is configured to connect the information handling system with the slave device, to receive a transmission power setting of the slave device while the first master device is connected to the slave device, to disconnect the from the slave device, and to continuously track a received signal strength indicator of the slave device while the first master is disconnected from the slave. The second master device configured to connect with the slave device in response to the first master device disconnecting from the slave device, wherein the connection to the second master causes the slave device to communicate with at least one more master device than the specific number of master devices.

Abstract: To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

Abstract: A plurality of system on chips (SoCs) in a server computer can be coupled to a plurality of memory agents (MAs) via respective Serializer/Deserializer (SerDes) interfaces. Each of the plurality of MAs can include one or more memory controllers to communicate with a memory coupled to the respective MA, and globally addressable by each of the SoCs. Each of the plurality of SoCs can access the memory coupled to any of the MAs in uniform number of hops using the respective SerDes interfaces. Different types of memories, e.g., volatile memory, persistent memory, can be supported.

Abstract: A system includes a central processing unit (CPU); main and auxiliary storage devices coupled to a plurality of memory ports; a memory bus suitable for coupling the CPU and the plurality of memory ports; and a memory controller suitable for, when the CPU calls data stored in the auxiliary storage device, controlling the called data to be transferred from the auxiliary storage device to the main storage device and stored in the main storage device.

Abstract: A computer-implemented method determines that a link operation associated with a first link, among the set of interface links in a computing system, has resulted in a first set of signal lanes, included in the first link, becoming unused. The method further includes determining a link configuration and selecting, based on the link configuration, a second link from among the interface links, and determining a second set of signal lanes, from among the unused signal lanes included in the first link, to include in the second link. The signal lanes to include in the second link are based on an attribute associated with the second link. The method further includes dynamically reconfiguring the signal lanes included in the second to set to be included in the lanes in the second link. Some computing systems include a lane routing device connected to signal lanes of links among the interface links.

Abstract: One or more virtual functions are exposed via a shared communication interface. Memory across said virtual functions is shared to provide a fixed number of I/O buffers shared across said virtual functions. For each of said one or more virtual functions, storing a corresponding map table configured to store a mapping data that maps a logical block address of the virtual function to a corresponding allocated one of said fixed number of I/O buffers based at least in part on a current state of a state machine.

Abstract: Methods and systems for a networked computing system are provided. One method includes generating a first proxy endpoint by a non-transparent bridge (NTB) of a first pluggable compute module and a second proxy endpoint at a second pluggable module having a second NTB, based on a user defined topology; establishing a transaction layer packet (TLP) tunnel between the first proxy endpoint and the second proxy endpoint for peer to peer communication using a first stub endpoint of the first NTB and a second stub endpoint of the second NTB; and de-allocating the first proxy endpoint and the second proxy endpoint, when the topology is deactivated such that the first pluggable compute module and the second pluggable module are available for another user defined topology.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.

Abstract: Methods and apparatuses relating to resolving roles for dual role serial bus devices are described. In one embodiment, an apparatus includes a serial bus receptacle to receive a serial bus plug of a device, a power supply electrically coupled to the serial bus receptacle, a multiple role toggling circuit to toggle the power supply between a power source role and a power sink role, wherein the device comprises a second power supply to toggle between a power source role and a power sink role, and a randomizer circuit to cause a plurality of different, toggling duty cycles and/or a plurality of different, toggling frequencies to be applied to the multiple role toggling circuit.

Abstract: A multi-sensing system (20) includes multiple sensor units (28) that include respective sensors (44), (ii) are connected to one another in a cascade using serial data lines (32), and (iii) are connected to a common clock line (36) and to a common alignment line (40). The sensor units are configured to selectably communicate in accordance with first and second different serial communication protocols using the same serial data lines, clock line and alignment line. A host (24) is configured to communicate with the sensor units, including reading the sensors and instructing the sensor units to switch between the first and second serial communication protocols.