Patents Examined by Dayton Lewis-Taylor
  • Patent number: 12038866
    Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: July 16, 2024
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Patent number: 12035068
    Abstract: A process includes, responsive to a computer platform being in a pre-operating system mode of operation, a first controller receiving serial data from a first external communication connector of the computer platform and the first controller providing a video output based on the serial data; and routing the video output of the first controller to a display device connector. The process includes, determining whether a video driver of the computer platform is communicating with a second controller via a second external communication connector of the computer platform. The video driver is associated with an operating system mode of operation of the computer platform. The process includes, in response to determining that the video driver is communicating with the second controller, routing a video output of the second controller to the display device connector in place of the video output of the first controller.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 9, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vincent W. Michna, Yasir Jamal, Peter A. Hansen
  • Patent number: 12033056
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, relating to multi-task recurrent neural networks. One of the methods includes maintaining data specifying, for a recurrent neural network, a separate internal state for each of a plurality of memory regions; receiving a current input; identifying a particular memory region of the memory access address defined by the current input; selecting, from the internal states specified in the maintained data, the internal state for the particular memory region; processing, in accordance with the selected internal state for the particular memory region, the current input in the sequence of inputs using the recurrent neural network to: generate an output, the output defining a probability distribution of a predicted memory access address, and update the selected internal state of the particular memory region; and associating the updated selected internal state with the particular memory region in the maintained data.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: July 9, 2024
    Assignee: Google LLC
    Inventors: Milad Olia Hashemi, Jamie Alexander Smith, Kevin Jordan Swersky
  • Patent number: 12032498
    Abstract: A hybrid storage device includes an interface configured to electrically couple the hybrid storage device to an external device, and exchange data with the external device, a plurality of storage channels electrically coupled to the interface and configured to exchange the data with the interface, a plurality of chip select lines, where each of the chip select lines is electrically coupled to one storage channel in the storage channels and configured to exchange the data with the one storage channel, and a plurality of storage medium particles, where each of the storage medium particles is electrically coupled to one chip select line and configured to exchange the data with the one chip select line. The storage medium particles include a non-volatile random-access memory (NVRAM) and a flash memory.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: July 9, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yongjun Xiao, Fei Kong, Jianfeng Geng, Biao He, Dengwei Xia, Guangyu Zhang
  • Patent number: 12023182
    Abstract: A portable patient-care kit is disclosed. The kit includes a housing, a plurality of compartments and a touch-screen user interface device. The housing forms a container space. The plurality of compartments is disposed within the container space such that each compartment is configured to retain at least one medical apparatus. The touch-screen user interface device has a transceiver that can communicate via a mobile data network.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: July 2, 2024
    Assignee: DEKA Products Limited Partnership
    Inventors: Jason A. Demers, Frederick Morgan, George W. Marchant, Jr., David E. Collins, Katie A. DeLaurentis, Dean Kamen
  • Patent number: 12026118
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: July 2, 2024
    Assignee: Google LLC
    Inventors: Nishant Patil, Liqun Cheng
  • Patent number: 12019580
    Abstract: Serial communication is performed at high speed by combining different communication methods. A communication device includes a communication unit configured to add, to a batch of data blocks including a serial signal group conforming to a serial peripheral interface (SPI) and transmitted from a master in synchronization with a clock, identification information for identifying the data blocks, and transmit the data blocks to a communication partner device within one frame period of a predetermined communication protocol, or add identification information for identifying each of a plurality of data blocks to the plurality of data blocks each including each part of the serial signal group, and transmit the data blocks to the communication partner device in a plurality of frame periods.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 25, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Toshihisa Hyakudai, Junya Yamada, Satoshi Ota
  • Patent number: 12013798
    Abstract: A method of data synchronization is to be implemented by a redundant server system including an active input/output module (IOM) and a passive IOM. The method includes: allocating a primary transfer buffer in the active IOM; allocating a secondary transfer buffer in the passive IOM; collecting pieces of secondary dedicated-sensor data, and storing the pieces of secondary dedicated-sensor data in the primary transfer buffer at once; collecting pieces of primary dedicated-sensor data; after the pieces of primary dedicated-sensor data have been collected, updating the primary state data based on the pieces of primary dedicated-sensor data thus collected and the pieces of secondary dedicated-sensor data stored in the primary transfer buffer at once, and storing the primary state data thus updated in the secondary transfer buffer; and updating the secondary state data based on the primary state data that have been updated and that are stored in the secondary transfer buffer.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: June 18, 2024
    Assignee: Mitac Computing Technology Corporation
    Inventors: Chin-Hung Tan, Heng-Chia Hsu, Chien-Chung Wang, Yu-Shu Yeh, Chen-Yin Lin
  • Patent number: 12007929
    Abstract: A processor having a system on a chip (SOC) architecture comprises one or more central processing units (CPUs) comprising multiple cores. An optical Compute Express Link (CXL) communication path incorporating a logical optical CXL protocol stack path transmits and receives an optical bit stream directly after the link layer, bypassing multiple levels of the CXL protocol stack. A CXL interface controller is connected to the one or more CPUs to enable communication between the CPUs and one or more CXL devices over the optical CXL communication path.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: June 11, 2024
    Assignee: Altera Corporation
    Inventors: Anshuman Thakur, Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Mahesh Kumashikar
  • Patent number: 12010045
    Abstract: The packet processing apparatus includes a packet memory, a transmission processing unit that writes a plurality of packets to be transmitted to the packet memory to generate a combination packet into which the plurality of packets have been concatenated, a line handling unit that sends packets to a communication line, and a combination packet transfer unit that DMA-transfers the combination packet from the packet memory to the line handling unit. The transmission processing unit writes information on an address in the packet memory of beginning data of an individual packet in the combination packet to a descriptor. The line handling unit separates the DMA-transferred combination packet into a plurality of packets and sends the plurality of packets to the communication line.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: June 11, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Tomoaki Kawamura, Shoko Oteru, Yuta Ukon, Shuhei Yoshida
  • Patent number: 12004062
    Abstract: The present disclosure discloses a management system, including a docking station device and a backend server. The docking station device includes an interface, a hub controller, a System on a Chip (SoC) control circuit, and an Internet-of-Thing (IoT) transceiver circuit. The interface is configured to receive a signal of an electronic device. The hub controller is configured to manage signal transmission between the electronic device and a host computer. The SoC control circuit is configured to perform an operating system to determine the type of the electronic device. The backend server includes a permission data. When the interface receives the signal, the interface sends the signal to the hub controller, and the hub controller determines whether the electronic device has high transmission speed. If no, the hub controller allows the signal transmission between the electronic device and the host computer.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: June 4, 2024
    Assignee: GOOD WAY TECHNOLOGY CO., LTD.
    Inventors: Tsu-I Peng, Chang-Der Liu, Cheng-Kang Tsui
  • Patent number: 11994853
    Abstract: The present disclosure relates to a control device for redundant execution of an operating function, wherein the control device comprises at least a first processor unit and a second processor unit and a plurality of peripheral units and a first switching unit is provided for the first processor unit and a second switching unit is provided for the second processor unit, and wherein the control device is designed in a first operating mode to execute the operating function by means of the first processor unit and in the meantime to execute a predetermined auxiliary function by means of the second processor unit.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 28, 2024
    Assignee: AUDI AG
    Inventors: Matthijs Paffen, Hans-Georg Gruber, Michael Schmailzl, Jürgen Isenberg, Reinhard Schieber, Jürgen Lerzer, Thorsten Zießler
  • Patent number: 11995020
    Abstract: A Peripheral Component Interconnect Express (PCIe) data transmission method includes a first node that obtains a transaction layer packet (TLP). The TLP includes a TLP header, a TLP extension header, and data. The TLP header includes a type field, an Fmt field, and a reserved bit, and where the type field, the Fmt field, the reserved bit, and the TLP extension header indicate a data type of the data and at least one piece of attribute information corresponding to the data type such that, information, the data type and the at least one piece of the attribute information, to transmit the data is indicated using the type field, the Fmt field, the reserved bit, and the TLP extension header in the TLP.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: May 28, 2024
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lei Wan, Pengxin Bao
  • Patent number: 11995011
    Abstract: Methods, systems, and devices for an efficient turnaround policy for a bus are described. A device may include a memory and a bus for communicating with the memory. The device may operate the bus in a first direction, relative to the memory, that is associated with a first type of access command. The device may determine, for the memory, that a quantity of queued access commands of a second type are for one or more banks that have satisfied a timing constraint for activating different rows in a same bank. Based on determining that the quantity of queued access commands of the second type are for one or more banks that have satisfied the timing constraint, the device may operate the bus in a second direction, relative to the memory, that is associated with the second type of access command.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: May 28, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Saira Samar Malik, Taeksang Song, Chinnakrishnan Ballapuram
  • Patent number: 11977506
    Abstract: A controller enumerates a plurality of devices while operating in a daisy-chain mode of operation and then causes the devices to operate in a parallel mode of operation in which the devices are individually addressed.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: May 7, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: James E. Heckroth, Patrick Johannus De Bakker, Ion Constantin Tesu, Phillip M. Matthews
  • Patent number: 11977503
    Abstract: A control device includes a memory, and a processor coupled to the memory, to a first communication bus, and to a second communication bus, the processor being configured to control whether or not to relay data communicated using the first communication bus to the second communication bus, and in a case in which a request has been received for data communicated using the first communication bus, execute switching so as to relay data received from the first communication bus to the second communication bus.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: May 7, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yusuke Kato, Seigo Takai
  • Patent number: 11977423
    Abstract: Methods and systems for thermal management of hardware resources that may be used to provide computer implemented services are disclosed. The disclosed thermal management method and systems may improve the likelihood of data processing systems providing desired computer implemented services by improving the thermal management of the hardware resources without impairment of storage devices. To improve the likelihood of the computer implemented services being provided, the systems may proactively identify whether storage devices subject to impairment due to dynamic motion are present. If such storage devices are present, then the system may automatically take action to reduce the likelihood of the storage devices being subject to dynamic motion sufficient to impair their operation.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: May 7, 2024
    Assignee: Dell Products L.P.
    Inventors: Hung-Pin Chien, Jyh-Yinn Lin, Yu-Wei Chi Liao, Chien Yen Hsu, Ming-Hui Pan
  • Patent number: 11972328
    Abstract: A machine learning device including a general-purpose memory module interface is disclosed. The machine learning device includes a data storage circuit configured to store raw data and command data received from a host device through a memory module interface, and store machine learning data as a result of machine learning of the raw data and location data of the machine learning data, a machine learning logic circuit configured to generate the machine learning data through the machine learning of the raw data according to a pre-programmed machine learning logic, and a machine learning controller configured to read the raw data from the data storage circuit based on the command data, transmit the read raw data to the machine learning logic circuit, and write the machine learning data and the location data in the data storage circuit.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 30, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Young Ahn
  • Patent number: 11971837
    Abstract: A processor interface assembly includes: a first interface circuit including a plurality of sub-interface circuits and configured to couple with a plurality of peripheral devices, wherein the plurality of peripheral devices is configured to occupy a pre-determined address space, and the pre-determined address space includes multiple sub-address spaces; and a controller including a register and configured to set a sub-address space occupied by at least one type of peripheral devices among the plurality of peripheral devices based on at least a portion of data stored in the register.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 30, 2024
    Assignee: PHYTIUM TECHNOLOGY CO., LTD.
    Inventors: Fudong Liu, Cai Chen, Lizheng Fan, Xiaofan Zhao
  • Patent number: 11971835
    Abstract: Techniques for creating and establishing a configuration of connections between an initiator system and a target system can use whitelisted target ports, wherein the configuration only includes connections to selected whitelisted target ports. Automatic login of each initiator to all zoned and discovered target ports can be avoided where, alternatively, an on-demand or needs-based login can be performed by having each initiator only log into its whitelisted target ports. In this manner, better resource usage and scalability can be obtained using the techniques of the present disclosure. In one embodiment, the whitelisted target ports can be determined automatically using an intersection of target port lists obtained using a control path connection and using a fabric nameserver query. The configuration including the whitelisted targets can be persistently stored on the initiator system to enable restoration of the whitelisted targets across reboots and resets of the initiator system.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 30, 2024
    Assignee: Dell Products L.P.
    Inventors: Prakash Venkatanarayanan, Matthew Long, Hari Prasad Chandrasekaran