Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.

Abstract: A computing device includes: a housing defining an exterior of the computing device; a controller supported within the housing; a first communication port disposed on the exterior; a second communication port disposed on the exterior; a port-sharing subsystem supported within the housing, having (i) a first state to connect the controller with the first communication port, exclusive of the second communication port, and (ii) a second state to connect the controller with the first communication port and the second communication port; the controller configured to: detect engagement of an external device with the first communication port; obtain connection parameters from the external device; based on the connection parameters, set the port-sharing subsystem in either the first state or the second state; and establish a connection to the external device via the port-sharing subsystem and the first communication port.

Abstract: An information handling system includes a processor having a first data storage device in a first memory tier, a second data storage device in a second memory tier, and a tiering manager. The first tier exhibits first data storage attributes and the second tier exhibits second data storage attributes. The tiering manager receives first memory access information from the first data storage device and second memory access information from the second data storage device, makes a determination that a first performance level of the information handling system when first data is stored in the first data storage device can be improved to a second performance level of the information handling system by swapping the first data to the second data storage device based upon the first memory access information and the second memory access information, and swaps the first data to the second data storage device in response to the determination.

Abstract: A data transmission control device is provided. The data transmission control device is disposed in a chip that includes a Peripheral Component Interconnect Express (PCIe) interface, and the data transmission control device is coupled to a memory that includes a block. The data transmission control device includes: a control circuit, a PCIe interface controller, and an address monitoring circuit. The PCIe interface controller is configured to receive a data. The address monitoring circuit is configured to issue an interrupt to the control circuit when the data is written to the block.

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.

Abstract: Systems and method for lane management in a communication bus are disclosed. In one aspects, a communication link or bus between a baseband processor (BBP) and a radio frequency integrated circuit (RFIC) may include multiple uplink lanes for transmission and multiple downlink lanes for reception that are frequency constrained and adjust bandwidth by adjusting duty cycles on the lanes. To reduce power consumption by the communication bus, exemplary aspects of the present disclosure contemplate using in-band signaling to turn off lanes selectively during inactive periods such that the lanes do not duty cycle in tandem with active lanes. Additionally, in some aspects, the uplink lanes may be continuously active during transmission while the downlink lanes are turned off. This dynamic lane usage reduces power consumption, does not require additional pins for sideband signaling, and does not introduce any additional latency.

Abstract: A data scaling module for USB4 that embodies display driver (DD) and connection manager (CM) operations. Periodic and aperiodic transfer requests are monitored. The periodic BW activity on periodic peripherals, such as display panels (DPs) is monitored, and determinations as to reduced periodic activity on a DP are made. Responsive to receiving a high aperiodic bandwidth request, the original refresh rate for the DP is reduced. The newly freed USB4 BW is provided for the aperiodic task. At completion of the aperiodic task, the DD increases the refresh rate to its original value.

Abstract: In one embodiment, an apparatus includes: a plurality of cores to execute instructions; a firmware agent to execute a first firmware; a Peripheral Component Interconnect Express (PCIe) interface to communicate with a device via a PCIe link; and a boot agent coupled to the PCIe interface to download the PCIe firmware from a non-volatile memory and provide the PCIe firmware to the PCIe interface. The PCIe interface may receive a PCIe firmware for the PCIe interface before the firmware agent is to receive the first firmware. Other embodiments are described and claimed.

Abstract: A data transmission method includes: obtaining a target data packet to be stored, the target data packet including an address of the target data packet; determining, from predetermined N parallel-to-serial units based on the address of the target data packet, a target parallel-to-serial unit corresponding to the target data packet, the N parallel-to-serial units being connected to N storage control units in one-to-one correspondence; and transmitting, by the target parallel-to-serial unit, the target data packet to a target storage control unit, and storing, by the target storage control unit, the target data packet in a corresponding storage unit. The target storage control unit is a storage control unit, connected to the target parallel-to-serial unit, of the N storage control units. The target parallel-to-serial unit is configured to divide the target data packet into a plurality of data sub-packets.

Abstract: A serial transmission controller for processing data transmissions between a memory and an external device is provided. The serial transmission controller includes a microcontroller, a scheduling unit, a transmission unit, and an interception control unit. The microcontroller obtains pipe data from the memory. The microcontroller reads a transfer request block from the memory according to the pipe data. The scheduling unit generates a transmission request according to the pipe data and the transfer request block. The transmission unit transmits a packet of the transfer request block according to the transmission request, and correspondingly generates a transmission response. When the interception control unit receives the transmission response, and the data length that has not been transmitted in the transfer request block is greater than 0, the interception control unit notifies the transmission unit to continue to transmit a next packet of the transfer request block.

Abstract: An electrical signal transmission method applied to an electrical signal transmission system includes first transmission interfaces and second transmission interface(s). Electrical signal transmission modes of the electrical signal transmission system include: a first transmission mode used for controlling a total transmission power of the first transmission interfaces and the second transmission interface(s) to be less than or equal to a first preset power, and a second transmission mode used for controlling a maximum transmission power of a second transmission interface to be the first preset power. The electrical signal transmission method includes: determining whether the first transmission mode is turned on; if yes, making the total transmission power of the first transmission interfaces and the second transmission interface(s) less than or equal to the first preset power; and if no, making the maximum transmission power of the second transmission interface be a second preset power.

Abstract: Embodiments of the present invention relates to an assembly unit having an electronic circuit unit which is accommodated in a housing, can be electrically connected to a higher-level switching system for signal and power supply purposes and comprises a signal processing unit for controlling consumer elements which are connected to the assembly unit, are installed within the housing or being virtual consumer elements-, wherein the signal processing unit comprises a plurality of units which are interact so as to allow, during operation, electrical disconnection of the assembly unit with load current-free electronic circuit unit from the state electrically connected to a higher-level switching system. Embodiments of the present invention also relates to a switching system comprising an assembly unit of this kind, and to a corresponding method.

Abstract: An electronic circuit device for acquiring an analog signal. The device comprising: a data line, one or more control lines (of which at least a clock line, and configured for transmitting a stored digital measurement result using the data line and the one or more control lines, in accordance with a synchronous serial communication protocol; a detection means for recognizing a synchronization pulse on one of the one or more control lines or on the data line; wherein the device is configured for repetitively measuring the analog signal or for measuring the analog signal triggered by the synchronization pulse; and for storing one or more digital measurement results or combinations thereof when triggered by the synchronization pulse.

Abstract: An inspection apparatus, which inspects a CAN communication function of an ECU, comprises: a connection unit which connects a communication circuit of the ECU and the inspection apparatus on a one-to-one basis; a creation unit which creates an inspection message in which a predetermined signal level is set in a confirmation field of a data format corresponding to a message received from the ECU; a transmission unit which transmits the inspection message to the ECU; a reception unit which receives a response message to the inspection message from the ECU; a confirmation unit which confirms whether a signal level of the confirmation field in the response message is changed with respect to setting of the inspection message; and a determination unit which determines whether a reception function of the ECU is normal based on the confirmation.

Abstract: Collaborative environments can allow multiple users access to view and modify objects. In order to avoid conflicting requests from different users to modify objects in the environment, virtual semaphore objects can be made available to users in a collaborative environment. A virtual semaphore can confer an ability to edit or modify objects in the environment, upon being assigned to a user. Users can request changes to user-semaphore assignments, including summoning a semaphore to be self-assigned, surrendering a self-assigned semaphore, transferring a semaphore from one user to another, and scheduling a semaphore assignment to a particular user at a future time. Upon assignment to a particular user, a virtual semaphore can be moved to a location close to a virtual representation of the particular user. Users can request changes to user-semaphore assignments using input devices by making selections in a graphical user interface, or by performing gestures associated with virtual semaphores.

Abstract: The present disclosure relates to a semiconductor memory device including various types of memories to which a host is connected. The semiconductor memory device in one implementation includes a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory; a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory; and an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory.

Abstract: Digitally controllable elements capable of influencing operation of a power amplifier module are coupled to an interface gateway device using a first serial data interface that communicates using a first serial protocol. The interface gateway device receives serial data on multiple external serial data interfaces that utilize various serial protocols, and converts the various serial protocols to the first serial protocol. Each digitally controllable element includes address control logic that decodes an address presented on the first serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written.

Abstract: The disclosure provides a bus-based communication system, which comprises a bus controller, a first buffer, a bus redundant controller, a second buffer and a comparator. The bus controller is configured to receive a bus input signal and send a bus output signal. The first buffer is connected with the bus controller in parallel to receive the bus input signal, and is configured to output the bus input signal after a preset time, wherein the preset time is two or more duty cycles of the bus controller. The bus redundant controller is connected to an output terminal of the first buffer and configured to receive a bus output signal delayed by at least T cycles output by the first buffer and output a bus redundant output signal.

Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.