Patents Examined by Dayton Lewis-Taylor
  • Patent number: 11650754
    Abstract: Embodiments of the present disclosure provide a data accessing method, a device and a storage medium. The method includes: obtaining a first accessing request and a second accessing request for a storage device; loading first data associated with the first accessing request from a source device to a pre-allocated buffer area with a size same as a size of a single physical storage block of the storage device; determining a first part of the second data when the first size of second data associated with the second accessing request is greater than or equal to the second size of an available space of the buffer area, a size of the first part being the same as the second size; and providing the first data and the first part to a target device associated with the first accessing request and the second accessing request.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: May 16, 2023
    Inventors: Zihao Liang, Jian Ouyang
  • Patent number: 11615046
    Abstract: The present application relates to a bus communication signal conversion method and device, a medium, and a numerical control machine tool control equipment. The bus communication signal conversion method comprises: acquiring an interface type of a bus interface of a first equipment end; receiving an output signal sent by a communication interface of a second equipment end; extracting a working parameter value of the second equipment end from the output signal; and sending the working parameter value of the second equipment end to the bus interface of the first equipment end according to a communication protocol corresponding to the interface type. The use of the present method can achieve signal conversion between different types of interfaces, thereby ensuring effectiveness of communication.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: March 28, 2023
    Inventors: Yuxin Feng, Yan Chen, Yunfeng Gao
  • Patent number: 11604747
    Abstract: Systems and methods for communication between heterogenous processors via a virtual network interface implemented via programmable hardware and one or more buses. The programmable hardware may be configured with a multi-function bus such that the programmable hardware appears as both a network device and a programmable device to a host system. Additionally, the programmable hardware may be configured with a second bus to appear as a network device to an embedded system. Each system may implement network drivers to allow access to direct memory access engines configured on the programmable hardware. The configured programmable hardware and the network drivers may enable a virtual network connection between the systems to allow for information transfer via one or more network communication protocols.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 14, 2023
    Assignee: National Instruments Corporation
    Inventors: Patrick Karl Sisterhen, Ashish S. Chaudhari, Moritz Daniel Fischer, Daniel Paul Jepson, Hector M. Rubio, Andrew Michael Lynch, Klaus Martin Braun, Antonia Marie Walls Jones
  • Patent number: 11604754
    Abstract: A method and apparatus of integrating memory stacks includes providing a first memory die of a first memory technology and a second memory die of a second memory technology. A first logic die is in communication with the first memory die of the first memory technology, and includes a first memory controller including a first memory control function for interpreting requests in accordance with a first protocol for the first memory technology. A second logic die is in communication with the second memory die of the second memory technology and includes a second memory controller including a second memory control function for interpreting requests in accordance with a second protocol for the second memory technology. A memory operation request is received at the first or second memory controller, and the memory operation request is performed in accordance with the associated first memory protocol or the second memory protocol.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: March 14, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dmitri Yudanov, Michael Ignatowski
  • Patent number: 11599621
    Abstract: Systems, methods, and apparatuses relating to performing an attachment of an input-output memory management unit (IOMMU) to a device, and a verification of the attachment. In one embodiment, a protocol and IOMMU extensions are used by a secure arbitration mode (SEAM) module and/or circuitry to determine if the IOMMU that is attached to the device requested to be mapped to a trusted domain.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Rajesh Sankaran, Abhishek Basak, Pradeep Pappachan, Utkarsh Y. Kakaiya, Ravi Sahita, Rupin Vakharwala
  • Patent number: 11593284
    Abstract: An embodiment method for managing an operation for modifying the content of the memory plane of a memory device coupled to a processing unit, comprises a communication by the processing unit to the memory device of a control of the operation, an execution of the operation by the memory device, and at the end of the operation, a communication by the memory device itself to the processing unit of information indicating the end of the operation.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 28, 2023
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Gilles Dionis
  • Patent number: 11574172
    Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Dipanjan Sengupta, Jawad B. Khan, Theodore Willke, Richard Coulson
  • Patent number: 11568296
    Abstract: According to an embodiment of the present invention, a quantum processor includes a qubit chip. The qubit chip includes a substrate, and a plurality of qubits formed on a first surface of the substrate. The plurality of qubits are arranged in a pattern, wherein nearest-neighbor qubits in the pattern are connected. The quantum processor also includes a long-range connector configured to connect a first qubit of the plurality of qubits to a second qubit of the plurality of qubits, wherein the first and second qubits are separated by at least a third qubit in the pattern.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: January 31, 2023
    Inventors: Dongbing Shao, Markus Brink, Martin O. Sandberg, Vivekananda P. Adiga
  • Patent number: 11561923
    Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: January 24, 2023
    Assignee: Oracle International Corporation
    Inventors: Navaneeth P. Jamadagni, Ji Eun Jang, Anatoly Yakovlev, Vincent Lee, Guanghua Shu, Mark Semmelmeyer
  • Patent number: 11550693
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for logging real-time data of a robot control system.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: January 10, 2023
    Assignee: Intrinsic Innovation LLC
    Inventors: Michael Beardsworth, Marcin Krzysztof Szczodrak, Gregory J. Prisament
  • Patent number: 11526461
    Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: December 13, 2022
    Assignee: Renesas Electronics America Inc.
    Inventors: Ahmad Nasser, Tobias Belitz
  • Patent number: 11513979
    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
  • Patent number: 11483511
    Abstract: An information processing device includes a processor, a plurality of connectors that output video signals to a plurality of connected external displays, a plurality of detectors that detect connection states of the plurality of connectors to the plurality of external displays, a plurality of switches that switch paths between a plurality of output ports and the plurality of connectors, and a controller that controls a switching operation of the plurality of switches. The controller has setting information that defines a relationship between the connection states of the plurality of connectors and at least one connector that outputs at least one of video signals among the plurality of connectors, and controls a switching operation of the plurality of switches based on the connection states detected by the plurality of detectors and the setting information. The setting information is set by the user.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: October 25, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hironori Ueda, Shinya Sato
  • Patent number: 11474735
    Abstract: An operation method of a storage device configured to communicate with an external device through an interface channel includes receiving an indicator of a first throttling level of a plurality of throttling levels from the external device, setting a first operation parameter based on a throttling predefined table (PDT) including a relationship between the plurality of throttling levels and a plurality of throttling performances, such that the interface channel has a first throttling performance from among the plurality of throttling performances, the first throttling performance corresponding to the first throttling level, receiving a first input/output (I/O) request from the external device through the interface channel having the first throttling performance caused by the setting of the first operation parameter, and processing a first operation corresponding to the first I/O request through the interface channel having the first throttling performance.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: October 18, 2022
    Inventors: Sangwon Jung, Jinsoo Yoo, Hyeongyu Cho
  • Patent number: 11474788
    Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: October 18, 2022
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Tanmoy Roy, Anuj Grover, Giuseppe Desoli
  • Patent number: 11455575
    Abstract: A multi-dimensional mesh architecture is proposed to support transmitting data packets from one source to a plurality of destinations in multicasting or broadcasting modes. Each data packet to be transmitted to the destinations carries a destination mask, wherein each bit in the destination mask represents a corresponding destination processing block in the mesh architecture the data packet is sent to. The data packet traverses through the mesh architecture based on a routing scheme, wherein the data packet first traverses in a first direction across a first set of processing blocks and then traverses in a second direction across a second set of processing blocks to the first destination. During the process, the data packet is only replicated when it reaches a splitting processing block where the paths to different destinations diverge. The original and the replicated data packets are then routed in different directions until they reach their respective destinations.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 27, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Dan Tu, Enrique Musoll, Chia-Hsin Chen, Avinash Sodani
  • Patent number: 11449455
    Abstract: During operation, the system receives, by a master node, a first I/O request with associated data, wherein the master node is in communication with a first plurality of storage drives via a switch based on a network protocol, wherein the master node and the first plurality of storage drives are allowed to reside in different cabinets, and wherein a respective collection of storage drives are coupled to a converter module, which is configured to convert data between the network protocol and an I/O protocol used to access the storage drives. The system identifies, by the master node, a first collection of storage drives from the first plurality on which to execute the first I/O request. The system executes, based on a communication via the switch and a converter module associated with the first collection of storage drives, the first I/O request on the first collection of storage drives.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: September 20, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11436185
    Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 6, 2022
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Patent number: 11435937
    Abstract: Facilitating monitoring of service processors associated with a data storage system is provided herein. A system can include a monitoring component and an interpretation component. The monitoring component monitors a service processor that controls one or more functions for a data storage system. The monitoring component also generates trend data indicative of trend information for the service processor. The interpretation component performs one or more actions associated with the data storage system in response to a determination that the trend data satisfies a set of defined criteria associated with monitored conditions for the data storage system.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeffrey D. Esposito, Michael P. Blanchard
  • Patent number: 11436182
    Abstract: A multiplexor for an Improved Inter-Integrated Circuit (I3C) network includes a switch, a snooper, and an I3C slave module coupled to an I3C master interface. The switch selectably couples I3C busses to the I3C master interface. Each I3C bus incudes I3C slave interfaces. The selected I3C bus is the active bus, and the non-selected I3C busses are inactive buses. The snooper detects In-Band Interrupts (IBIs) from the I3C slave interfaces coupled to the inactive buses. When the snooper receives a first IBI on an inactive bus, the snooper provides an indication. The I3C slave module provides a second IBI to the I3C master interface in response to the indication.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 6, 2022
    Assignee: Dell Products L.P.
    Inventors: Jordan Chin, Timothy M. Lambert