Patents Examined by Debra A. Chun
  • Patent number: 5293498
    Abstract: An arrangement of a designation of a drive element number using mother boards interposed between an upper grade device and a plurality of drive elements includes a plurality of groups of drive elements, each of which drive elements has a specifically designated drive element number, an upper grade device for carrying out a signal communication through tag bus line cables with a selected drive element, and a plurality of mother boards interposed between the upper grade device and the plurality of drive elements, each of the mother boards corresponding to one of the plurality of groups of drive elements. The plurality of mother boards has a same potential level arrangement of connection pins for a drive element number designation in connecting portions.
    Type: Grant
    Filed: April 19, 1993
    Date of Patent: March 8, 1994
    Assignee: Fujitsu Limited
    Inventor: Masahito Iwatsubo
  • Patent number: 5293490
    Abstract: A data buffering device having a data buffer permitting data storage in a first storage area A while the area A is advanced over a predetermined number of storage areas of the buffer in a predetermined sequence and permitting data reading from a second storage area B while the area B is advanced in the same sequence; a first device judging whether or not it is permissible to carry out at least one of a simple data storage and a simple data reading; a second device executing, if the judgement of the first device is negative, a return judgement whether or not it is necessary to return a corresponding one, or each, of the areas A and B to a leading storage area of the buffer, and a possibility judgement whether or not the buffer has at least a predetermined number of storage area or areas permitting a corresponding one, or each, of a data storage and a data reading, if the possibility judgement is affirmative the second device placing the first device in a condition in which the first device provides an affirmat
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: March 8, 1994
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Ichiro Sasaki, Kouzi Nakayama
  • Patent number: 5291606
    Abstract: In an interrupt controller, interrupt processing mode indication circuits are provided for each interrupt request circuit for storing interrupt processing mode information, and priority level indication circuits are provided for each interrupt request circuit, for storing acknowledgement order information. A search information generating circuit is provided each for generating interrupt processing mode search information and priority order search information. A search information comparison circuit detects the state of the interrupt request circuit provided for each interrupt request memory circuit, and compares the processing mode information and the acknowledgement order information with the interrupt processing mode search information and priority order search information.
    Type: Grant
    Filed: March 30, 1992
    Date of Patent: March 1, 1994
    Assignee: NEC Corporation
    Inventors: Sachiko Okayama, Tsuyoshi Katayose
  • Patent number: 5289587
    Abstract: A microprocessor's program counter is made available external to the device on a dedicated bus. Thus, an emulator can readily generate a list of executed instruction addresses by monitoring the bus. This eliminates the conventional requirement of monitoring system bus traffic and attempting to extract and reconstruct the instruction execution sequence.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: February 22, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Bruce B. Razban
  • Patent number: 5289586
    Abstract: A digital information transmission apparatus and an information transmission bus system thereof capable of quickly stabilizing a signal on a bus. The apparatus outputs to a bus, in a bus cycle identical to a bus cycle in which a digital information input system reads desired digital information, information items identical to the desired digital information read by the digital information input system respectively from the buffers of at least two digital information output systems of a plurality of digital information output systems.
    Type: Grant
    Filed: August 27, 1992
    Date of Patent: February 22, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Umekita, Masatsugu Kametani
  • Patent number: 5287484
    Abstract: A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system.
    Type: Grant
    Filed: November 13, 1992
    Date of Patent: February 15, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Osamu Nishii, Kunio Uchiyama, Hirokazu Aoki, Takashi Kikuchi, Yasuhiko Saigou
  • Patent number: 5283899
    Abstract: A data processing system that includes several ongoing processes that provide input words to a buffer of an independently executing processor, a buffer manager that controls the process access to the buffer and controls the words input by the processes to the buffer that includes an apparatus for regulating the number of words from an executing first process for loading into the buffer, an apparatus for loading the number of words, an apparatus for loading a synchronization word when a second process is to be executed and an apparatus for halting the loading of the first process words and providing for loading of the second process words when the synchronization word is accessed by the independently executing processor.
    Type: Grant
    Filed: November 25, 1992
    Date of Patent: February 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: John A. Cook, Gregory A. Flurry, Larry W. Henson
  • Patent number: 5283906
    Abstract: A notebook computer CMOS firmware processing method and the related hardware for saving power consumption by means of the application of the internal functions of CMOS and the processing of CMOS firmware permitting keyboard to enter idle mode or power down mode when CPU is temporarily stopped from execution, or to wake up when any key is pressed or any command is sent from the system to the keyboard.
    Type: Grant
    Filed: October 22, 1991
    Date of Patent: February 1, 1994
    Assignee: Silitek Corporation
    Inventor: Cheng-Wen Chen
  • Patent number: 5283886
    Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively.
    Type: Grant
    Filed: September 24, 1992
    Date of Patent: February 1, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Osamu Nishii, Kunio Uchiyama, Hirokazu Aoki, Kanji Oishi, Jun Kitano, Susumu Hatano
  • Patent number: 5283869
    Abstract: A communications interface circuit couples a host processor to a pair of serial communications links. A shared memory is employed to pass message data and network management data between the host and the interface circuit, and each can interrupt the other through interrupt control lines. The shared memory stores a handshake segment that includes interrupt flags and acknowledge flags which enable a large number of different interrupt events to be efficiently serviced.
    Type: Grant
    Filed: July 25, 1989
    Date of Patent: February 1, 1994
    Assignee: Allen-Bradley Company, Inc.
    Inventors: Shawn L. Adams, Jonathan R. Engdahl
  • Patent number: 5280592
    Abstract: A pipeline interlock mechanism which insures the logical integrity of architected control quantities when used to access Domain Storage from Control State. A hardware Domain Interlock (DOMI) is provided to detect the start of execution in Control State of any instruction which modifies architected controls governing the access of Domain storage, and which insures that any subsequent potential access to Domain storage remains interlocked in the D-cycle until the modified controls become valid.
    Type: Grant
    Filed: January 3, 1992
    Date of Patent: January 18, 1994
    Assignee: Amdahl Corporation
    Inventors: Edward G. Ryba, Theodore C. Bernard
  • Patent number: 5280623
    Abstract: An improved computer system bus is disclosed that transitions between addressed data transfers and handshake data transfers on the fly and that performs burst within dynamic data sizing during a data transfer sequence without prematurely terminating the sequence and that changes between synchronous and asynchronous data transfer sequences on the fly. These capabilities are accomplished by modifying the function of bus signal lines depending upon the type of transfer sequence undertaken. On the fly transition between addressed data transfer and handshake data transfer is accomplished by providing a set of DMA acknowledge signals and modifying their function according to the type of data transfer sequence underway. Burst within dynamic data sizing during a sequence is performed by taking advantage of burst transfer capabilities of the slave device, and the capability of the master device to modify data width on the fly.
    Type: Grant
    Filed: March 4, 1992
    Date of Patent: January 18, 1994
    Assignee: Sun Microsystems, Inc.
    Inventors: Martin Sodos, Thomas Chan
  • Patent number: 5278959
    Abstract: A processor specially adapted for use as a coprocessor The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor operates as a bus master or a bus slave. Certain outputs pins have three-state bus drivers which employ feedback to ensure that a signal on a line being driven by the driver has gone inactive before the driver is turned off. Instructions executed by the microprocessor permit specification of portions of the internal registers as sources and destinations and specification of the size of an ALU operation, permitting easy operation on data ranging from bytes through 24-bit pointers. Instructions are executed in an instruction pipeline and a separate I/O instruction pipeline.
    Type: Grant
    Filed: March 13, 1993
    Date of Patent: January 11, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Gary T. Corcoran, Robert C. Fairfield
  • Patent number: 5276886
    Abstract: In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclosed. Each semaphore is one bit wide and can be written to obtain the desired state. When reading the semaphore, if the contents is a one, then a one is returned. If the content is zero, a zero is returned but the semaphore is automatically reset to one.
    Type: Grant
    Filed: October 11, 1990
    Date of Patent: January 4, 1994
    Assignee: Chips and Technologies, Inc.
    Inventor: Asael Dror
  • Patent number: 5276806
    Abstract: Independent heterogeneous computers are interconnected for oblivious, high speed, long distance communications. A printed circuit board with onboard RAM repeats all write commands through a data transmission media to a remote system. Each read and write cycle of the communicating computer is completed locally (using only local RAM). Apart from repeating write commands to a remote system, the invention is oblivious to the remote system. Data is transmitted from one machine to another without expensive communication protocols or transmission line latency induced wait states. A remote computer accesses network data only after it has been transmitted and stored in local memory. Multiple data transfers can be pipelined, that is, multiple datum may simultaneously reside in a high latency network/long transmission line. Although the time required to transmit any single datum remains proportional to the signal propagation delay, the time required to transmit multiple data is significantly reduced.
    Type: Grant
    Filed: September 19, 1988
    Date of Patent: January 4, 1994
    Assignee: Princeton University
    Inventors: Jonathan S. Sandberg, Richard J. Lipton
  • Patent number: 5276863
    Abstract: A process for providing access to the console functionality of a computer system in response to console function requests. A console server computer system and a console client computer system are in a network, and console functions requests are included in data packets transmitted from the console client to the console server on a standard network interconnection. A console server computer system operating in an ON state is able to interrupt access to the operating system in response to the receipt of a data packet including a remote reset request, and can respond to console function requests without entering the console state.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: January 4, 1994
    Assignee: Digital Equipment Corporation
    Inventor: Gerhard K. Heider
  • Patent number: 5274822
    Abstract: A fast centralized arbitrator for avoiding contention between up to eight processors or other smart devices having access to a shared computer facility. Each of the processors or smart devices is assigned a unique three digit octal formatted priority level. A first set of 1-of-8 decoders, AND gates and a prioritizer circuit are employed to determine the priority level of the highest priority device requesting access to the shared facility. A second set of 1-of-8 decoders, each having associated therewith a set of OR gates for combining the decoder outputs with the outputs of the prioritizer circuit and an AND gate for combining the outputs of the set of OR gates, are employed to generate a set of acknowledge signals for the smart devices.
    Type: Grant
    Filed: July 2, 1990
    Date of Patent: December 28, 1993
    Assignee: NCR Corporation
    Inventors: Richard L. Stanton, Kenneth J. Kotlowski
  • Patent number: 5274823
    Abstract: A method for serializing access to computer system resources without disabling interrupts in critical code sections or requiring excessive use of spin locks. A queue lock is introduced that allows an interrupt process to enqueue and be processed in turn without a spin lock and to block process code access to a particular resource until all interrupts are processed. Process level code is blocked from accessing a locked resource while requests for accesses from interrupt level code are queued in a deferred work queue which is processed prior to the release of the blocking lock. Establishment of deferred work queue means that processing can continue without disablement of interrupts and without significant overhead consumed by processes holding spin locks.
    Type: Grant
    Filed: March 31, 1992
    Date of Patent: December 28, 1993
    Assignee: International Business Machines Corporation
    Inventors: Larry B. Brenner, Barry P. Lubart, Jeffrey S. Lucash, John C. Rathjen, Jr., Ronald Sasala, Thomas Van Weaver
  • Patent number: 5274773
    Abstract: A high level controller for maintaining communication with a host processor via a host processor interface for establishing communication paths between the host processor interface, an internal processor and a plurality of storage means. A first means receives indicia from the internal processor where the indicia specifies one of the communication paths and generates control signals for forming the specific communication path requested. A second means receives the control signals from the first means and forms the requested communication path. A third means is connected to the first and second means for controlling the communication of the system with the host processor interface in accordance with control signals generated by the first means. In this manner various data paths for communication between the host interface, internal processor and a plurality of storage means may be adaptably specified and formed to make optimum use of the system.
    Type: Grant
    Filed: December 29, 1992
    Date of Patent: December 28, 1993
    Assignee: Conner Peripherals, Inc.
    Inventors: John P. Squires, Charles M. Sander, Stanton M. Keeler, Donald W. Clay
  • Patent number: 5274824
    Abstract: In a distributed data system in which processes running in trusted systems whose results may be proprietary or sensitive in nature may be invoked by operators at remote, untrusted workstations, and in which said processes are provided with locks which do not permit proprietary or sensitive actions unless a request includes a key matching the lock, a method of associating keys with operators is based on each operator's presenting his ID and a valid password at the workstation at the time he logs on to the system, verifying his password in a trusted system, correlating his ID with a role or group of roles he is authorized to fulfill, and retrieving and storing in the memory of the trusted system, associated with the operator's ID, a list of keys (a "keyring") for each of those roles. The operator's ID is appended to every request he invokes, a process containing a lock interrogates the stored list and will not grant a proprietary action unless the stored list contains a key matching the lock.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: December 28, 1993
    Assignee: Bull HN Information Systems Inc.
    Inventor: David I. Howarth