Patents Examined by Debra A. Chun
  • Patent number: 5274764
    Abstract: A continuous data input control system for an optical disk comprising an optical disk digital signal processor for outputting serial data, beat clock signal and left/right clock signal, an optical disk ROM decoder for decoding and transmitting the data from the processor, a microprocessor for controlling the whole system, and a data input controller for controlling the output of the digital signal processor. The data input controller includes a clock generator, a counter, a first control signal generator, an AND gate, a stop point detector for shifting the serial data of the digital signal processing unit by synchronization with the clock pulse signal of an AND gate, for latching the data when the buffer RAM is in the overflow state in response to the output level of the control signal generating unit, and for detecting the data of the stop point by comparing the latched data with the data being presently inputted, when the overflow of the buffer RAM is released.
    Type: Grant
    Filed: March 13, 1991
    Date of Patent: December 28, 1993
    Assignee: Goldstar Co., Ltd.
    Inventor: Dae Y. Kim
  • Patent number: 5274828
    Abstract: A computer system includes a data processor, an address bus, a data bus, and a read only memory device interconnected with the data processor by way of the address and data buses. A random access memory device also is interconnected with the data processor by way of the address and data buses. The random access memory device includes an on-chip voltage supply, a node for connecting with a second voltage supply, and a selection circuit, arranged to be selectively enabled for supplying charge to a load circuit from either the second voltage supply or the on-chip voltage supply. Voltage V.sub.pp, applied to the load circuit from the on-chip voltage supply, has been boosted to a magnitude that is higher than the voltage V.sub.dd of the second voltage supply. Charge supplied by the combination of the second voltage supply and the on-chip voltage supply is less than the charge used by a single on-chip boosted voltage supply.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: December 28, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Hugh P. McAdams
  • Patent number: 5265211
    Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus.
    Type: Grant
    Filed: January 2, 1992
    Date of Patent: November 23, 1993
    Assignee: International Business Machines Corporation
    Inventors: Nader Amini, Bechara F. Boury, Richard L. Horne, Terence J. Lohman
  • Patent number: 5265216
    Abstract: A bus interface coupling an asynchronous bus and a slave device, such as a memory. The bus interface comprises an asynchronous bus controller and a synchronous bus controller. The asynchronous bus controller is implemented as two PAL state machines. One state machine controls the connection and disconnection phases of the bus protocol, while the other controls the data transfer phase. The synchronous bus controller controls data transfer between the bus and the slave device. The state machines are closely interlinked to each other and the synchronous bus controller allowing for increased bus efficiency.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: November 23, 1993
    Assignee: Digital Equipment Corporation
    Inventors: Ciaran P. Murphy, Tadhg Creedon, Con D. Cremin
  • Patent number: 5265256
    Abstract: A data processing system (10) has programmable normal and low voltage modes of operation. The normal voltage mode of operation enables precharge transistors (32, 34) to couple a voltage of (V.sub.DD -V.sub.tn) to each of a plurality of precharge circuit nodes, such as precharge bus (30), within data processing system (10). During the low voltage mode of operation, the full V.sub.DD is coupled to each precharge circuit node, wherein the power supply voltage during the low voltage mode of operation is reduced. Data processing system (10) has a voltage mode bit (36) for receiving voltage mode information from a source external to data processing system (10). In response to an active logic state within voltage mode bit (36), a low voltage mode clocking circuit (42) is enabled.
    Type: Grant
    Filed: July 1, 1991
    Date of Patent: November 23, 1993
    Assignee: Motorola, Inc.
    Inventors: Kin K. Chau-Lee, Phil P. D. Hoang
  • Patent number: 5264958
    Abstract: The interface subsystem comprises a universal interface card or unit for use with any of a plurality of electrical interface standards, for example, EIA-232-D, and CCITT Recommendations V.35 and X.21. The interface subsystem further comprises a cable selected from a set of cables for use with the particular standard being utilized. The particular cable has preconditioning means so that the signals conforming to the corresponding interface standard are within a voltage-level window suitable for the universal interface unit for processing. The universal interface unit comprises an input/output port for receiving the preconditioned signals having common pins among the interface standards. The preconditioned signals are routed to one or more receivers for converting the signals to TTL level for processing by a communications processor.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: November 23, 1993
    Assignee: International Business Machines Corp.
    Inventor: Daniel W. J. Johnson
  • Patent number: 5265218
    Abstract: A bus architecture and protocol for integrated data and video memory. A high speed dedicated memory bus is coupled to a memory controller. The memory controller is in turn coupled to a multiple processor bus interconnecting one or more processors. Single in-line memory modules (SIMMs) incorporating dynamic random access memory (DRAM), video RAM (VRAM), and static nonvolatile RAM (SRAM) are coupled to the memory bus. Bus control signals forming a bus protocol, and address and data lines from the memory controller are shared by all memory modules operating on the memory bus. Certain control signals invoke specific operations on memory modules or are ignored, depending on the type of memory module receiving the control signal. The memory modules incorporate the consistent protocol by virtue of a consistent control signal pin out. The SIMMs further incorporate buffering and conversion functions, thereby relieving the memory controller of service overhead associated with these functions.
    Type: Grant
    Filed: May 19, 1992
    Date of Patent: November 23, 1993
    Assignee: Sun Microsystems, Inc.
    Inventors: James Testa, Andreas Behtolsheim, Edward Frank, Trevor Creary, David Emberson, Shawn F. Storm, Bradley Hoffert
  • Patent number: 5263145
    Abstract: A method and means for managing access to a logical track of KN blocks of which K are parity blocks. The KN blocks are distributed and stored in an array of N DASDs having K blocks per physical track per DASD. The array includes control means for securing synchronous access to selectable ones of the DASDs responsive to each access request. The method involves (a) formatting the blocks onto the array using a row major order modulus as the metric for balancing the data rate and concurrency (the number of DASDs bound per access) and (b) executing the random sequences of large and small access requests over the array.
    Type: Grant
    Filed: May 24, 1990
    Date of Patent: November 16, 1993
    Assignee: International Business Machines Corporation
    Inventors: James T. Brady, Ruth E. Cintron, Stephen Goldstein, Jean H. Wang Ju, Jaishankar M. Menon
  • Patent number: 5263138
    Abstract: An auxiliary busing arrangement for transferring real time data in a computer system including a plurality of conductors sufficient to transfer in parallel the bits of a data word and the control signals necessary to control the transfer; a plurality of components connected to utilize the busing arrangement, each of the components being assigned a unique priority number and being connected to one of the plurality of conductors used for one of the control signals; apparatus in each of the components for detecting the condition of the one of the plurality of conductors; apparatus for providing clock signals on another of the plurality of conductors used for one of the control signals; apparatus for providing a first condition on the one of the plurality of conductors; apparatus in each of the components for providing a second condition on the one of the plurality of conductors; apparatus in each of the components for terminating an attempt to access the busing arrangement in response to the detection of the sec
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: November 16, 1993
    Assignee: Apple Computer, Inc.
    Inventors: Steven Wasserman, Steven Roskowski
  • Patent number: 5263147
    Abstract: A security system 31 for use with a base computer system 29 includes an access monitoring unit 100 for continuously monitoring all operations in the memory address space, the input/output address space, or both, of the base computer 1 in parallel with base computer execution. The access monitoring system 100 can include access monitoring memory tables which specify, for a given user, his read access and write access to data stored in the security system, in the base computer system or both.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: November 16, 1993
    Assignee: Hughes Training, Inc.
    Inventors: Emmanuel C. Francisco, Randy Saunders
  • Patent number: 5261059
    Abstract: An interface between a host computer and a crossbar switch is provided which employs data buffering using multiple-port RAM devices. The receive and transmit data is clocked into or out of separate serial ports of the RAM, and at the same time a local processor can access the RAM by a random access port, asynchronous to the serial ports, to execute the protocol. The order of storing bursts of data in the multiple-port RAM is defined by a free buffer manager which keeps account of which locations are free. The addresses of these locations are moved to a received list after being used for incoming packets. After the protocol processor has finished with its tasks, these addresses, referred to as burst data descriptors, are moved to a transmit list to await loading of burst data back to the serial registers for clocking out, then when transmitted the descriptors are again entered into the free buffer manager.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: November 9, 1993
    Assignee: Digital Equipment Corporation
    Inventors: William F. Hedberg, Martin G. Halvorson, Donald B. Ellsworth, Jr., Richard E. Lewis, Paul T. Brooks, Gary H. Mendelsohn
  • Patent number: 5261058
    Abstract: A disk drive architecture controls the transfer of data between a host processor interface and a recording media that includes one or more disk surfaces for storing data. A low-level data controller controls the transfer of data between the disk surfaces and a data buffer. An interface controller controls the transfer of data between the host interface and the data buffer. An arbiter and buffer controller, responsive to data transfer requests from the low-level and interface controllers, arbitrates data storage and retrieval accesses of the data buffer. The low-level and interface controllers operate substantially independent of one another in performing their respective control operations. Consequently, data is transferred bi-directionally through the data buffer at the optimum timing for both controllers.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: November 9, 1993
    Assignee: Conner Peripherals, Inc.
    Inventors: John P. Squires, Charles M. Sander, Stanton M. Keeler, Donald W. Clay
  • Patent number: 5261084
    Abstract: In a method of judging a data memory access error in an information processing apparatus, the data memory access error flag is set in the process state register upon occurrence thereof, and an error flag in the process state register is set until updating of the process state register and until clearing by a software instruction. The data memory access errors are stored in the general registers in units of operation levels, and data memory access error judging is executed upon detection of the error flag under the control of software.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: November 9, 1993
    Assignee: NEC Corporation
    Inventors: Tatsuro Hashiguchi, Atsushi Takahashi
  • Patent number: 5257374
    Abstract: The flow of work requests in a server driven process to process communication environment is described. Logical connections between processes and bus managers interfacing bus units to an I/O bus are assigned to connection groups for management by the bus managers. Each bus unit has its own connection groups for the logical connections. Bus unit resources are assigned to each connection group based on performance factors, and a series of bus unit messages are used to control the flow of work so that a group which has no more resources will not accept further work requests. The originator of the work requests will resequence rejected work requests and resend them when the connection group has freed up resources. A further mechanism is provided to facilitate work consistent with the server driven architecture when bus units do not have adequate DMA capabilities. Two ways of reversing control of transfer of work requests and data so that the server need not have master DMA capability are presented.
    Type: Grant
    Filed: May 24, 1991
    Date of Patent: October 26, 1993
    Assignee: International Business Machines Corporation
    Inventors: William E. Hammer, Walter H. Schwane, Frederick J. Ziecina
  • Patent number: 5257383
    Abstract: A programmable, multi-level interrupt priority encoder which fields interrupts from connected devices, e.g., DMA engine, scanner, and timer, and signals an interrupt value, or priority level, associated with that device. These levels, which may range from zero to seven or more, depending upon the system with which it is applied, are used by the CPU to determine which of the plural interrupting devices to service. Using the encoder of the invention, multiple devices can be set at the same priority level.
    Type: Grant
    Filed: August 12, 1991
    Date of Patent: October 26, 1993
    Assignee: Stratus Computer, Inc.
    Inventor: Joseph M. Lamb
  • Patent number: 5255376
    Abstract: An improved high speed bus and protocol are disclosed that are capable of transferring data in multiple modes. The bus is particularly useful in computer systems that require data transfer between a variety of computer peripheral memory devices. In base transfer mode, the bus is capable of a maximum of 32-bit data transfers while in extended transfer mode, the bus is capable of a maximum of 64-bit data transfers. The bus comprises a plurality of lines including address lines, size lines, data lines and various control lines. In its extended transfer mode, the bus is capable of employing a number of address and control lines as data transfer lines. The bus is also capable of disabling a device when the device is accessed in a transfer mode that the device does not support.
    Type: Grant
    Filed: January 14, 1992
    Date of Patent: October 19, 1993
    Assignee: Sun Microsystems, Inc.
    Inventor: Edward H. Frank
  • Patent number: 5255374
    Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit.
    Type: Grant
    Filed: January 2, 1992
    Date of Patent: October 19, 1993
    Assignee: International Business Machines Corporation
    Inventors: Alfredo Aldereguia, Nader Amini, Richard L. Horne, Terence J. Lohman, Cang N. Tran
  • Patent number: 5249284
    Abstract: A method and system of maintaining coherency for a data block transferred from a main memory to a cache memory. The data transfer is recorded in a tag register in the main memory. An overwrite of the data block is detected by comparing main memory data writes with the recorded transfer. The cache memory is only notified in the event an overwrite is detected. An invalid flag is then set in the cache.
    Type: Grant
    Filed: December 13, 1991
    Date of Patent: September 28, 1993
    Assignee: NCR Corporation
    Inventors: William J. Kass, Michael R. Hilley, Lee W. Hoevel
  • Patent number: 5249285
    Abstract: A memory system for use in a text entry system is provided. The system includes a retentive data memory and a system for locking a portion of the retentive memory and a key for unlocking the lockable portion of the memory to allow a predetermined number of bits of data to be written to the memory when the lockable memory is in unlocked state. The system automatically locks the memory after the predetermined number of bits have been written into the lockable portion of memory.
    Type: Grant
    Filed: July 23, 1992
    Date of Patent: September 28, 1993
    Assignee: Stenograph Corporation
    Inventors: David J. Mueller, Denis B. Flynn, Keith A. McCready, Paul G. Dussault
  • Patent number: 5247687
    Abstract: Paging data is used to manage address space working set size, system multiprogramming level, and job mix, to improve system productive CPU utilization. System paging characteristics are monitored to determine when to perform management functions. When needed, address space paging data is collected for monitored address spaces, and target working set sizes set for managed address spaces. If necessary, address spaces are "forced" to exhibit characteristic paging patterns. Reallocation of working set pages among active address spaces, and swap in-swap out actions, are assessed, and impacts on productive CPU utilization is estimated.
    Type: Grant
    Filed: August 31, 1990
    Date of Patent: September 21, 1993
    Assignee: International Business Machines Corp.
    Inventors: Catherine K. Eilert, Bernard R. Pierce