Patents Examined by Dharti H. Patel
  • Patent number: 11804710
    Abstract: The aim of the invention is to detect an arc in an assembly for transmitting a direct voltage. This aim is achieved by a communication transformer having a primary winding and a secondary winding, the secondary winding being connected to a transmitting device, which is designed to impress a communication signal onto the secondary winding of the communication transformer, and the primary winding being connected to one of the direct voltage lines in order to feed a communication signal transformed by the communication transformer to one of the direct voltage lines. In order to detect, in the assembly, the arc signal caused by an arc, the secondary winding is connected to an arc detection unit, which is designed to detect an arc signal transformed by the communication transformer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 31, 2023
    Assignee: FRONIUS INTERNATIONAL GMBH
    Inventors: Bernd Hofer, Christian Fasthuber, Franz Fischereder, Stefan Breuer, Walter Spitzer, Mario Bairhuber, Reimar Pfeil
  • Patent number: 11798936
    Abstract: The present disclosure provides electrostatic discharge circuits and structures and methods for operating the electrostatic discharge circuits and structures. A circuit includes a first transistor and a second transistor. The first transistor includes a drain, a source, a gate, and a bulk. The drain of the first transistor is connected to a first terminal. The source of the first transistor is connected to receive a first voltage. The gate and the bulk of the first transistor is connected to receive a second voltage. The second transistor includes a drain, a source, a gate, and a bulk. The source, the gate, and the bulk of the second transistor is connected to receive the second voltage. The drain of the second transistor is connected to the first terminal. In response to the terminal reaching a trigger voltage, the first transistor is configured to be turned on.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzu-Heng Chang, Hsin-Yu Chen, Pin-Hsin Chang
  • Patent number: 11799287
    Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: October 24, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ramkumar Sivakumar, Subbarao Surendra Chakkirala
  • Patent number: 11791626
    Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: October 17, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: You Li, Alain F. Loiseau, Souvick Mitra, Tsung-Che Tsai, Mickey Yu, Robert J. Gauthier, Jr.
  • Patent number: 11791625
    Abstract: The present invention relates to an electrostatic protection circuit for protecting an internal circuit. The electrostatic protection circuit includes: a first circuit connected between a power pad and an input pad and configured to discharge a first electrostatic current; a second circuit connected between the input pad and a ground pad and configured to discharge a second electrostatic current; a third circuit connected between the power pad and the input pad and configured to discharge a third electrostatic current; a fourth circuit connected between the power pad and the ground pad and configured to discharge a fourth electrostatic current; a fifth circuit connected between the input pad and the ground pad and configured to discharge a fifth electrostatic current; and a sixth circuit connected between the ground pad and the power pad and configured to discharge a sixth electrostatic current.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: October 17, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: QiAn Xu
  • Patent number: 11791624
    Abstract: Examples relate to an overvoltage protection circuit for a device interface adapted to convey at least electrical energy. The overvoltage protection circuit includes a first and a second terminal and a normally-on transistor. The normally-on transistor is electrically coupled to the first and second terminal. The overvoltage protection circuit further includes a control circuit configured to switch off the normally-on transistor as a function of at least one of a voltage at the first terminal and a voltage at the second terminal. Further examples relate to a device including an interface and an overvoltage protection circuit. The first terminal of the overvoltage protection circuit is electrically coupled to the interface.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: October 17, 2023
    Assignee: Infineon Technologies AG
    Inventors: Jie Fang, Heinrich Guenther Heiss
  • Patent number: 11791627
    Abstract: An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: October 17, 2023
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Qimeng Jiang, Yushan Li, Hanxing Wang
  • Patent number: 11785698
    Abstract: Provided is a static eliminator that efficiently eliminates static electricity from a tray of a droplet ejection device of a tray transport type. A static eliminator 20 includes a movable part 22 which is pushed by a tray 12 due to movement of the tray 12 and moves, and an ion generator 24 disposed on a movement path of the tray 12 and configured to generate ions according to the movement of the movable part 22.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: October 10, 2023
    Assignee: FUNAI ELECTRIC CO., LTD.
    Inventor: Takeshi Kobayashi
  • Patent number: 11776721
    Abstract: A superconducting magnet comprising: a field coil comprising high temperature superconducting material and having a joint; a bypass resistance comprising a non-superconducting conductive material, wherein the bypass resistance is electrically connected to the field coil on both sides of the joint; wherein the joint is openable to break the field coil such that current flowing in the superconductor flows though the bypass resistance in order to dump energy from the field coil, and wherein the superconducting magnet is configured to open the joint in response to detection of a quench in the magnet.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: October 3, 2023
    Assignee: Tokamak Energy Ltd
    Inventor: Robert Slade
  • Patent number: 11776457
    Abstract: The present disclosure provides an electrostatic protection circuit and a display panel, wherein the electrostatic protection circuit includes a first voltage reference unit configured to divide a voltage between an array substrate row driving signal line and a common electrode line once; a second voltage reference unit configured to divide the voltage between the array substrate row driving signal line and the common electrode line twice; and a charge releasing unit that adjusts charge distribution between the array substrate row driving signal line and the common electrode line based on reference voltages provided by the first voltage reference unit and the second voltage reference unit.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: October 3, 2023
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Yuzhi Li
  • Patent number: 11770000
    Abstract: An electronic control unit includes a microcontroller. The microcontroller includes a power supply pin configured to receive power and at least one input/output (I/O) pin. A voltage regulator includes a power input configured to connect to a power source and to a regulated power output connected to the power supply pin via an I/O fault protection circuit.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: September 26, 2023
    Assignee: Continental Automotive Systems, Inc.
    Inventor: Michael A. Haggerty
  • Patent number: 11769999
    Abstract: An apparatus for detecting an open neutral condition in a split phase power system is described. The apparatus includes two powered lines providing output electricity to an electrical distribution system and a shared neutral line providing a grounded neutral to the first and second powered lines. The apparatus is configured for detecting when an open neutral condition is present in the split phase power system by determining when a power current is present on one or both of the first and second powered lines while a return current is not present on the neutral line; and in response to detecting that the open neutral condition is present, causing an interrupter to interrupt the power supplied by the first and second powered lines or to generate a signal indicating an open condition.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: September 26, 2023
    Assignee: Southwire Company, LLC
    Inventors: Donald Paul Oldham, Jr., Hamze Moussa
  • Patent number: 11765810
    Abstract: Provided is a soft X-ray static electricity removal apparatus that has achieved an increase in the amount of ionized air discharged, with a simple structure. A soft X-ray static electricity removal apparatus (1) includes a soft X-ray generation device (90), a container (10), a soft X-ray shielding sheet (20), and an insulating layer (50). The soft X-ray generation device generates soft X-rays (92). The container (10) has an outlet (12) from which ionized air (100) that has been ionized with the soft X-rays flows out. The soft X-ray shielding sheet (20) is used at the outlet of the container and includes a first outer sheet (30), an interlayer sheet (34), and a second outer sheet (40) which are formed of a material opaque to the soft X-rays.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 19, 2023
    Assignee: Cambridge Filter Corporation
    Inventors: Toshiro Kisakibaru, Kouta Ueno, Makoto Yoshida, Nobuyuki Uesugi, Naoji Iida
  • Patent number: 11764572
    Abstract: A device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage at a first terminal and receive a second voltage at a second terminal and includes a first trigger circuit and a first resistor. The first trigger circuit includes a first input terminal and a first output terminal. The first input terminal is configured to receive the first voltage. The first resistor is coupled between the first output terminal and the second terminal. When the first voltage received at the first terminal is a first overvoltage and a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: September 19, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Hang Fan, Ming-Fang Lai, Shui-Ming Cheng
  • Patent number: 11742656
    Abstract: A surge protection device with a high breaking capacity includes a housing with at least two lead-out electrodes, and a voltage limiting device and a thermal tripping mechanism that are installed in the housing. The voltage limiting device includes a voltage limiter, a first electrode and a second electrode that are positioned and installed in an insulating cover. The thermal tripping mechanism includes a fixed assembly, a movable assembly and a thermal trigger device. The fixed assembly and the movable assembly form a plurality of displacement switches arranged in series. The thermal trigger device is disposed in linkage with the movable assembly and includes a metal trigger sheet, a fusible alloy and an energy storage member. One end of the metal trigger sheet is fixed on the movable assembly, and the other end of the metal trigger sheet is fixed on the second electrode through welding by the fusible alloy.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 29, 2023
    Assignee: XIAMEN SET ELECTRONICS CO., LTD.
    Inventors: Xianggui Zhang, Tian'an Gao
  • Patent number: 11733323
    Abstract: Described systems and methods allow the detection and quantitative estimation of changes in the properties of a liquid sample comprising living biological cells, the changes caused by exposure to a target analyte such as a toxin, drug, pesticide, etc. A variable stimulus such as an oscillating magnetic field is applied to the sample, inducing variations in a position or shape of a constituent of the sample. Such variations produce measurable variations in electric and/or optical properties of a sensor, variations which allow a precise quantification of changes due to exposure to the target analyte.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 22, 2023
    Assignee: Centrul International de Biodinamica
    Inventors: Eugen Gheorghiu, Mihai S. David, Mihaela Gheorghiu
  • Patent number: 11735578
    Abstract: An electrostatic discharge (ESD) protection circuit is configured to protect a target circuit that operates in a cryogenic temperature is provided. The ESD protection circuit connects a terminal of the target circuit and a ground potential with no connection to a bias potential. When the ESD protection circuit receives a voltage potential at the terminal of the target circuit, the ESD protection circuit (i) disallows electrical current to flow through from the received voltage potential when the device is at a cryogenic temperature and (ii) allows electrical current to flow through from the received voltage potential when the device is at a room temperature.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: August 22, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peter Mueller, Thomas Morf, Mridula Prathapan, Matthias Mergenthaler
  • Patent number: 11728642
    Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventors: Shigefumi Ishiguro, Yasuhiro Suematsu, Takeshi Miyaba, Kimimasa Imai, Maya Inagaki
  • Patent number: 11728228
    Abstract: A display substrate and a display apparatus are provided, the display substrate includes: a base substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixel units in the display area; a plurality of data lines in the display area and electrically coupled to the plurality of sub-pixel units; a plurality of data transmission lines in the peripheral area on at least one side of the display area and electrically coupled to the plurality of data lines; a plurality of first pads and a plurality of second pads located between the plurality of first pads and the plurality of data transmission lines; a plurality of third pads between the plurality of first pads and the plurality of second pads; and a plurality of multiplexers between the plurality of second pads and the plurality of third pads.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: August 15, 2023
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mengmeng Du, Xiangdan Dong, Hongwei Ma, Biao Liu, Bo Zhang
  • Patent number: 11728649
    Abstract: Disclosed is a reactance-injecting module and its method of use to balance the currents among the phases of polyphase electric power transmission lines or to manage power flow among alternate paths, where the reactance-injecting module has high-speed, dedicated communication links to enable the immediate removal or reduction of injected reactance from all phases of a phase balancing cluster when a fault is detected on any one of the multiple phases. The reactance-injecting module may communicate information on a detected fault to the other reactance-injecting modules of the phase balancing cluster within 10 microseconds after the fault is detected to allow the phase balancing cluster to eliminate injected reactance from all phases within a time that is short compared to a cycle of the alternating current, such as 1 millisecond after the fault is detected. This provides extremely fast neutralization of injected reactance to minimize interference with fault localization analyses.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: August 15, 2023
    Assignee: Smart Wires Inc.
    Inventors: Leonard J. Kovalsky, Hamed Khalilinia, Niloofar Torabi, Michael T. Garrison Stuber, Sana Tayyab, Adeel Ahmad Khan, Haroon Inam