Abstract: In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.

Abstract: Embodiments described herein provide foreign object detection based on coil current sensing. The transmitter power loss is computed directly based on the coil current, in conjunction with, or in place of the conventional computation based on transmitter input current. The enhanced precision of the computer power loss can be used to more accurately detect a foreign object near the transmitter coil during a wireless power transfer.

Abstract: An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.

Abstract: A comparing device includes a first current generating circuit arranged to selectively generate a first current and a second current different from the first current, according to a first control signal. The comparing device also includes a comparing circuit having a common node coupled to the first current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

Abstract: A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.

Abstract: According to at least one aspect, a filter network is provided. The filter network comprises: an active filter comprising an amplifier (e.g., an operational amplifier), wherein the active filter is configured to add at least one member selected from the group consisting of a pole and a zero to a transfer function of the filter network; a passive filter coupled to the active filter and configured to add at least one pole to the transfer function of the filter network; and a non-inverting amplifier (e.g., a voltage buffer) having an input coupled to the passive filter and an output coupled to the active filter.

Abstract: Provided is a reference voltage circuit including a Zener diode having a cathode connected to a current source via a first node, and an anode connected to a ground point; a first resistor having one end connected to the first node; a second resistor having one end connected to another end of the first resistor; a first diode having an anode connected to another end of the second resistor via a second node, and a cathode connected to the ground point; and a current control circuit configured to generate a control current corresponding to an anode voltage of the first diode so that the current source supplies a reference current corresponding to the control current to the first diode.

Abstract: A semiconductor device includes an inverter circuit having a first switching element and a second switching element, a first control circuit, a second control circuit, and a limiting unit. The first switching element is supplied with a power supply voltage. The second switching element includes a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal. The first control circuit controls the first switching element. The second control circuit controls the second switching element. The limiting unit reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element.

Abstract: A clock generator includes a first phase-locked loop (PLL), a converter circuit, and a second PLL. The first PLL generates an oscillating signal based on a reference signal and outputs a noise signal indicating a noise component of the oscillating signal. The converter circuit produces an electrical signal based on the noise signal. The second PLL receives the electrical signal from the converter circuit at a loop filter of the second PLL and generates a clock signal based on the oscillating signal and the electrical signal.

Abstract: A charge pump structure is disclosed. In an embodiment a regulated charge pump structure includes an output terminal configured to provide a regulated output voltage, a first charge pump configured to generate the output voltage as a function of an input supply voltage and a control circuit configured to limit a level of the output voltage and to generate a control voltage, wherein the level of the output voltage is controlled by the control voltage such that the output voltage does not exceed a threshold value.

Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.

Abstract: A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

Abstract: An all-digital closed-loop fine-grained control of voltage and frequency for running conditions of a compute machine such as graphic processor unit (GPU), central processing unit (CPU), or any other processing unit. The scheme optimizes the voltage margin and frequency on the fly according to desired programmable performance metrics. A mitigation response to droops is naturally built into the system and is equal to the cause rather than being excessive. The scheme is scalable and can be instantiated in different clusters for best results.

Abstract: A phase locked loop circuit includes a phase comparator that compares phases of a reference signal through a first frequency divider and a local signal through a second frequency divider to output a phase comparison signal; a loop filter that smooths the phase comparison signal to output the control voltage signal; a controller that sets frequency division ratios of the first and the second frequency dividers; a free-running voltage generator that generates a free-running voltage signal of the voltage control oscillator; a measurement circuit that measures a voltage of the control voltage signal; a storage circuit that stores therein the voltage of the control voltage signal; and a low-pass filter that transmits, to the voltage control oscillator, a corrected free-running voltage signal based on a free-running voltage correction value calculated by the free-running voltage generator based on the control voltage signal before the frequency division ratios are changed.

Abstract: A signal generation circuit includes a first delay circuit, a second delay circuit, and a duty control circuit. The first delay circuit delays a first input signal to generate a first output signal. The second delay circuit delays a second input signal to generate a second output signal. The duty control circuit compares phases of the first and second output signals and changes the value of the second delay control signal, and then decreases the times, by which the first and second input signals are delayed, by the same value.

Abstract: A power converter is disclosed. The power converter includes a Single-Input-Multiple-Output (SIMO) device includes a first transistor connected to an input and a first end of an inductor, a second transistor connected to a second end of the inductor and a first output, and a third transistor connected to the second end of the inductor and a second output. The power converter also includes a controller connected to the SIMO device and is configured to maintain a minimum inductor current through the inductor between charging cycles and to cause the minimum inductor current to transition to a charging inductor current during a charging cycle. The charging inductor current is based on a difference between an output voltage signal and a target voltage signal.

Abstract: An ultra-low-power voltage reference generator in an integrated CMOS circuit includes a regular MOS transistor reference current source connected to a line voltage and a regular MOS transistor resistor between the regular MOS transistor reference current source and ground. A constant with temperature reference voltage VREF is generated from a terminal inter-connecting the regular MOS transistor reference current source and the regular MOS transistor resistor. An ultra-low-power current reference generator receives a reference voltage and generated ultra-low level current from the reference voltage with a temperature compensated gate-leakage array.

Abstract: An apparatus is disclosed for a charge pump with voltage tracking. In an example aspect, the apparatus includes a locked loop having a charge pump, a filter, a second switch, and a buffer. The charge pump includes a first current source, a second current source, and a first switch coupled between the first current source and the second current source. The filter is coupled to the charge pump between the first switch and the second current source. The second switch is coupled to the charge pump between the first current source and the first switch. The buffer is coupled between the filter and the second switch, with the buffer comprising a voltage buffer.

Abstract: Circuits and devices related to switch controller. In some embodiments, a radio-frequency module can include a packaging substrate configured to receive a plurality of components, and a switching circuit implemented on the packaging substrate. The radio-frequency module can further include a control circuit configured to control operation of the switching circuit. The control circuit can include a regulator configured to generate a plurality of reference voltage levels for the operation of the switching circuit, or to be in a sleep mode, based on a control signal received through a common input node. The control circuit can further include a mode detector in communication with the regulator and configured to provide a first form of the control signal to the common input node to allow the plurality of reference levels to be generated by the regulator, or a second form of the control signal to the common input node to put the regulator in the sleep mode.