Abstract: Embodiments include methods and systems of neuron leaky integrate and fire circuit (NLIFC). Aspects include: receiving an input current having both AC component and DC component at an input terminal of the NLIFC, extracting AC component of input current, generating a number of swing voltages at a swing node using extracted AC component of the input current, transferring charge from a pull-up node to a neuron membrane potential (NP) node through an integration diode and a pull-up diode to raise a voltage at NP node over an integration capacitor gradually and the voltage at NP node shows integration value of AC component of input current, implementing leaky decay function of the neuron leaky integrate and fire circuit, detecting a timing of neuron fire using an analog comparator, resetting a neuron membrane potential level for a refractory period after neuron fire, and generating fire output signal of the NLIFC.

Abstract: According to various aspects, a latch-type charge pump may include: an input node and an output node; a first charge storage and a second charge storage coupled in parallel to each other, a first switch coupled to the input node and a second switch coupled to the output node, wherein the first charge storage couples the first switch with the second switch; and a control circuit configured to control the first switch based on a state of the second charge storage, and to control the second switch based on a state of the first charge storage.

Abstract: A phase locked loop having a charge pump is described. The charge pump has circuitry to select a mode for each semiconductor chip from a plurality of modes to enhance yield. Nine unique modes are defined from which a selection is made for each chip. The selected mode mitigates effects of device mistracking anomalies for each chip. A method is provided to show how the modes are determined and prioritized.

Abstract: Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of Tpp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay Tdelay after the pre-pulse switch has been opened.

Abstract: A circuit includes first through fifth transistors. The first transistor has a first control input and first and second current terminals. The second transistor has a second control input and third and fourth current terminals. The third transistor has a third control input and fifth and sixth current terminals. The third control input is coupled to the third current terminal, and the fifth current terminal is coupled to a supply voltage node. The fourth transistor has a fourth control input and seventh and eighth current terminals. The fourth control input is coupled to the first current terminal, and the seventh current terminal coupled to the supply voltage node. The fifth transistor has a fifth control input and ninth and tenth current terminals. The fifth control input is coupled to the first control input, and the tenth current terminal coupled to the second current terminal.

Abstract: A power transistor is switched on and off with an on-time that is held constant and an off-time that is varied. When the off-time is detected to be less than a threshold value that is greater than a minimum off-time limit, the on-time is extended. Then the power transistor is switched on and off with the extended on-time that is held constant and the off-time that varies.

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

Abstract: Provided is a semiconductor device including a normally-off transistor having a first electrode, a second electrode, and a first control electrode, a normally-on transistor having a third electrode, a fourth electrode, and a second control electrode, a first capacitor having a first end and a second end, a Zener diode having a first anode and a first cathode, a first resistor having a third end and a fourth end, a first diode having a second anode and a second cathode, a second resistor having a fifth end and a sixth end, a second diode having a third anode and a third cathode, and a second capacitor having a seventh end and an eighth end.

Abstract: Measuring a control system response time of a second clock tree is provided, comprising measuring a skew between the second clock signal and the first clock signal and storing the skew, initiating a delay change of a delay induced by the programmable delay line and starting a time measurement. At least one iteration is performed of measuring the skew between the second clock signal and the first clock signal and comparing the measured skew with the stored skew. Based on the result of the comparison, stopping after a current iteration and stopping the time measurement. A result of the time measurement is the control system response time.

Abstract: Various implementations described herein are related to a device having level shifter circuitry configured to receive isolation control signals in a first voltage domain and provide an output signal in a second voltage domain that is different than the first voltage domain. The device may include isolation logic circuitry configured to receive a data input signal in the first voltage domain and then provide the isolation control signals to the level shifter circuitry in the first voltage domain based on the data input signal. The isolation logic circuitry may include control passgates that enable the data input signal to propagate to the level shifter circuitry via the isolation control signals.

Abstract: A frequency synthesizer system may include a first voltage-controlled oscillator (VCO) circuit, a second VCO circuit, and multiplexing circuitry. The multiplexing circuitry may be configured to select either the output of the first VCO circuit or the output of the second VCO circuit in response to a mode selection signal.

Abstract: A charge pump generates an output voltage. A first circuit generates a pulse width-modulated signal as a function of a deviation between the output voltage and a setpoint voltage. A second circuit receives a periodic signal and conditions the supply of the periodic signal to a control input of the charge pump as a function of the state of the pulse width-modulated signal.

Abstract: High-saturation power Josephson ring modulators and fabrication of the same are provided. A Josephson ring modulator can comprise a plurality of matrix junctions. Matrix junctions of the plurality of matrix junctions can comprise respective superconducting parallel branches that can comprise a plurality of Josephson junctions operatively coupled in a series configuration. A method can comprise forming a first matrix junction comprising arranging a first group of Josephson junctions as first parallel branches. The method can also comprise forming a second matrix junction comprising arranging a second group of Josephson junctions as second parallel branches. Further, the method can comprise forming a third matrix junction comprising arranging a third group of Josephson junctions as third parallel branches. In addition, the method can comprise forming a fourth matrix junction comprising arranging a fourth group of Josephson junctions as fourth parallel branches.

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

Abstract: A frequency adjusting apparatus used in a processing chip operated at an operation frequency according to a power is provided that includes a clock supplying circuit, a frequency division circuit and a control circuit. The clock supplying circuit outputs one of clock signals as a supplied clock signal. The frequency division circuit performs frequency division on the supplied clock signal according to a parameter to generate an output clock signal. The control circuit determines a combination of a selected clock signal and a value of the parameter for gradually increasing the frequency of the output clock signal during the increasing of the voltage value that passes through voltage value sections, wherein when the voltage value is determined to be larger than a second threshold value and when the voltage value sections correspond to higher voltage values, the selected clock signal has a higher frequency.

Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.

Abstract: A system for generating an RFPWM signal comprises a delta sigma modulator having a plurality of outputs, a phase-locked loop comprising a plurality of phase quantization outputs, at least one multiplexer having a plurality of signal inputs, a plurality of selector inputs, and at least one output, the signal inputs communicatively connected to the phase quantization outputs of the phase-locked loop and the selector inputs electrically connected to the outputs of the delta sigma modulator, and a driver having an input communicatively connected to the output of the multiplexer and an output generating an RFPWM signal. A method of generating an RFPWM signal is also described.

Abstract: Embodiments relate to sensing a current provided by a power supply circuit. The current sensing circuit includes a sense transistor for sensing the current provided by a main transistor, a driver for controlling a bias provided to the sense transistor and the main transistor, and a sense resistor for converting the sensed current to a voltage value. Moreover, the current sensing circuit includes a controller that modifies at least one of: (a) a resistance of the main transistor by adjusting the bias voltage provided by the driver, (b) a gain ratio between a load current and a sensing current by adjusting a number of individual devices that are active in the sense transistor, and (c) a resistance of the sense resistor.

Abstract: A voltage-source converter, VSC, control system including an active damper, AD, a direct-voltage controller, DVC, and an alternating-voltage controller, AVC. The VSC control system is configured to control a VSC. The AVC is configured to regulate, using an integrator, an ac-bus voltage of the VSC by calculating a q component of a current reference vector for the VSC. The DVC is configured to regulate, using an integrator, a dc-bus voltage of the VSC by calculating a d component of the current reference vector. The AD is configured to amplify a vectoral difference between the ac-bus voltage and a corresponding reference, and to add the q component of the amplified vectoral difference to the q component of the current reference vector and to an input of the integrator of the AVC.

Abstract: A delay locked loop (DLL) circuit includes inputs from M-phase clocks, M is an integer that is greater than or equal to 1; N delay cells in each of M separate delay lines, one delay line for each of the inputs from the M-phase clocks, and each of the N delay cells having a delay of k*?t, N is an integer, and k is an integer that is coprime with both N and M; N outputs for clock phases from the N delay cells; and an alignment circuit connected to outputs of the M separate delay lines and the inputs from the M-phase clocks and configured to provide phase locking.