Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.

Abstract: The memory device includes a substrate, a first ball grid array, a first integrated circuit chip, and a first electrostatic discharge protection element. The first ball grid array is disposed on the substrate. The first integrated circuit chip is disposed on the first ball grid array. The first electrostatic discharge protection element is coupled between the second input/output pad of the first integrated circuit chip and the first internal circuit. The first electrostatic discharge protection element is configured to form a first electrostatic discharge path from the second input/output pad to a first voltage supply line. The first electrostatic discharge protection element includes multiple electrostatic discharge units, and at least one of the electrostatic discharge units is free of coupling between the second input/output pad, the first voltage supply line, and the first internal circuit.

Abstract: A module is provided that includes a substrate having a first main surface, a first component mounted on the first main surface, a first sealing resin disposed so as to cover the first main surface and the first component, and a shield film covering at least an upper surface of the first sealing resin. The shield film includes a conductive layer, a first protective layer covering the conductive layer, and a second protective layer. The first protective layer is locally formed with a marking section. The second protective layer includes a first region covering the first protective layer and a second region covering the marking section.

Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.

Abstract: A display device and a method of manufacturing the same are provided. The display device comprises a first area which extends in a first direction, a second area which extends in the first direction and is alongside the first area in a second direction intersecting the first direction, at least one first light emitting element in the first area, at least one second light emitting element in the second area, at least one first wiring coupled to an end of the first light emitting element in the first area and that extends in the first direction and at least one second wiring coupled to an end of the second light emitting element in the second area and that extends in the first direction, wherein the first wiring and the second wiring are electrically isolated from each other.

Abstract: Embodiments of structures and methods for forming three-dimensional (3D) memory devices are provided. In an example, a 3D memory device includes a core region and a staircase region. The staircase region includes a plurality of stairs each has at least a conductor/dielectric pair extending in a lateral direction. The staircase region includes a drain-select-gate (DSG) cut structure extending along the lateral direction and a vertical direction, and a plurality of support structures extending in the DSG structure along the vertical direction. Of at least one of the support structures, a dimension along the lateral direction is greater than a dimension along a second lateral direction perpendicular to the lateral direction.

Abstract: A flexible display device and an electronic device are provided. The flexible display device includes: a flexible display panel; a plurality of functional members on a side of the flexible display panel, including a first functional member, a second functional member, and a third functional member; a back film on the other side of the flexible display panel; a supporting member on a side of the back film away from the flexible display panel; and a plurality of adhesive layers, including a first adhesive layer, a second adhesive layer, a third adhesive layer, a fourth adhesive, and a fifth adhesive layer. The third functional member includes a touch module including a touch substrate, a sensor layer, and an adhesive material layer between the sensor layer and the touch substrate, the modulus of the adhesive material layer is not less than the modulus of each of five adhesive layers.

Abstract: A semiconductor device includes an inductance structure and a shielding structure. The shielding structure is arranged to at least partially shield the inductance structure from external electromagnetic fields. The shielding structure includes a shielding structure portion arranged along a side of the inductance structure such that the shielding structure portion is around at least a portion of a perimeter of the inductance structure.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a device layer having a front-side surface opposite a back-side surface. A first heat dispersion layer is disposed along the back-side surface of the device layer. A second heat dispersion layer underlies the front-side surface of the device layer. The second heat dispersion layer has a thermal conductivity lower than a thermal conductivity of the first heat dispersion layer.

Abstract: Disclosed is a packaging method for circuit units, wherein the circuit units comprise a silicon layer substrate and a silicon dioxide layer overlaid on the silicon layer substrate. The packaging method for a circuit unit comprises: attaching a plurality of circuit units to a circuit baseplate in a spaced and inverted mode, wherein the silicon dioxide layer is attached to the circuit baseplate, and the silicon layer substrate faces away from the circuit baseplate; forming an insulator between the circuit units; removing the silicon layer substrate to expose the silicon dioxide layer; and forming an electromagnetic shielding layer on the silicon dioxide layer and the insulator.

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.

Abstract: An organic light-emitting diode device and a manufacturing method thereof are provided. The organic light-emitting diode device includes an array substrate, a light-emitting layer and a thin-film encapsulation layer stacked in order from bottom to top. The thin-film encapsulation layer includes a first inorganic layer, an organic layer and at least one dielectric structure layer in a stack. There is the dielectric structure layer is disposed in the thin-film encapsulation layer.

Abstract: A light-emitting module includes a light-emitting panel which includes a first rigid substrate, a flexible substrate, a circuit layer, a light-emitting element, and a driver chip. The flexible substrate includes a light-emitting region, a bending region, and an epitaxial region, and the light-emitting region and the epitaxial region are located on two ends of the bending region. The circuit layer includes a first connection terminal located on the epitaxial region and the driver chip is bonded to the first connection terminal. The light-emitting element is located on the light-emitting region, and the light-emitting element emits light toward the first rigid substrate. The flexible substrate is bent in the bending region and the flexible substrate in the epitaxial region is bent to a side of the light-emitting elements facing away from the first rigid substrate. The process difficulty can be reduced and the product yield can be improved.

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

Abstract: A vertical memory device includes a cell stacked structure on a substrate, a support structure and cell contact plugs. The cell stacked structure includes gate patterns spaced apart from each other in a vertical direction and insulation layers between the gate patterns. The gate patterns extend in a first direction, and edges of the gate patterns along the first direction include step portions having step shape. The support structure passes through the cell stacked structure and the step portion of one of the gate patterns, and includes a spacer layer having cup shape, first metal patterns having ring shape, and a second metal pattern filling an inner space of the spacer layer. The cell contact plugs are on the step portions. The first metal patterns are at the same vertical levels of the gate patterns. Sidewalls of the first metal patterns are adjacent to sidewalls of the gate patterns.

Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, a conductive layer in contact with upper ends of the plurality of channel structures, at least part of which is on the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer.

Abstract: This present disclosure provides a manufacturing process of light emitting device and a light emitting device. The manufacturing process of light emitting device includes: step S1, making a quantum dot film; step S2, providing a LED unit, the LED unit including at least one LED chip; step S3, disposing a first transparent adhesive layer on an exposed surface of each LED chip; step S4, disposing the quantum dot film on the surface of the first transparent adhesive layer far away from the LED chip.