Abstract: A load control device for controlling the amount of power delivered to an electrical load is able to operate in a normal mode and a burst mode. The load control device may comprise a control circuit that activates an inverter circuit during active state periods and deactivates the inverter circuit during inactive state periods. The control circuit may operate in the normal mode to regulate an average magnitude of a load current conducted through the electrical load to be above a minimum rated current. The control circuit may operate in the burst mode to adjust the average magnitude of the load current to be below the minimum rated current. The control circuit may adjust the average magnitude of the load current by adjusting the length of the inactive state periods while holding the length of the active state periods constant.

Abstract: Methods and apparatuses are provided for establishing operational states of a device having a plurality of functional operating units. An input is configured to receive an identifier of a desired operational state of the device. A number of control outputs are configured to couple to one or more of the plurality of functional operating units having two or more operational states. A number of reference inputs are each configured to receive a reference signal, and at least one reference signal is mapped, based on the identifier, to at least one control output. Each control output provides a control signal that places each functional operating unit in a selected state to achieve the desired operational state of the device.

Abstract: There is provided a light control circuit including a detected voltage generating circuit, a reference voltage generating circuit, an error amplifier, an NMOS driver and a light source. The detected voltage generating circuit outputs a detected voltage to a first input terminal of the error amplifier. The reference voltage generating circuit outputs a reference voltage to a second input terminal of the error amplifier. The NMOS driver changes a drive current of the light source according to an output of the error amplifier.

Abstract: This disclosure relates to systems and methods adjusting lighting system brightness in a non-linear manner. The brightness control may be based on a non-linear function that increases brightness in smaller increments at lower brightness levels than at higher brightness levels. In another embodiment, the lighting system brightness may be ramped down over a period of time to account when the user device is exposed to low light conditions. The ramp down may be based, at least in part, on changes in visual acuity in low light conditions over time.

Abstract: An illustrative bi-level dimming controller for coupling to a dimming control input of a lighting driver includes a dimming preset selector for setting a preset dim level, and a dimming control circuit having variable impedance and providing a constant dimming voltage output for a preset dim level, even if the current supplied to or impedance coupled to the dimming controller changes. The dimming control circuit is responsive to the preset dim level to drive a dimming voltage output proportional to the preset dim level. The dimming controller may also include a dim enable circuit responsive to a detection signal to selectively couple and uncouple the dimming signal output with the dimming control input of the lighting driver, thereby providing switching between a preset dim level and a full light level. The detection signal may be electrically isolated from the dimming voltage output.

Abstract: A system comprising: one or more road-side illumination sources arranged to emit illumination to illuminate at least part of a road; one or more detectors arranged to detect a value of one or more parameters of a vehicle travelling on this road or this part of the road, the one or more parameters comprising a type of the vehicle and/or an identity of one or more users of the vehicle; and a controller arranged to control the illumination emitted by the one or more illumination sources, wherein the controller is configured to adapt the illumination in dependence on the detected value or values of the one or more detected parameters.

Abstract: A physically unclonable function unit includes and anti-fuse transistor and a control circuit. The anti-fuse transistor has a first terminal, a second terminal, and a gate terminal. The control circuit is coupled to the anti-fuse transistor. During an enroll operation, the control circuit applies an enroll voltage to the gate terminal of the anti-fuse transistor and applies a reference voltage to the first terminal and the second terminal of the anti-fuse transistor. The enroll voltage is higher than the reference voltage, and is high enough to create a rupture path on the gate terminal to the first terminal or to the second terminal.

Abstract: A processor unit can be used to rapidly search a string of characters. The processor unit can include vector registers each having M vector elements, each vector element having n bits of data for containing an encoded character. An M×M matrix of comparators within the processor unit can be used to compare elements of a first register storing a reference string and elements of a second register storing a target string. A logic gate is associated with each diagonal of the matrix of comparators, and is configured to combine the results of comparators along the diagonal, resulting in a bit vector indicating characters of the target string that fully match the reference string and characters that partially match the reference string. Correction logic within the processor unit can suppress indications of a partial match or of a full match in the bit vector.

Abstract: Large fan-in logical gate circuits for use in reciprocal quantum logic (RQL) systems and related methods permit for improved efficiency and density of RQL logic. A majority 3-of-5 gate circuit, as described, can be extended to include more than five inputs, and can also be modified to create AND gates, OR gates, and OA gates. The gate circuits can accommodate inputs and provide outputs each in the form of single flux quantum (SFQ) pulses, either positive or negative, to indicate asserted and de-asserted logic states, respectively.

Abstract: Techniques facilitating on-chip supply noise voltage reduction and/or mitigation using local detection loops in a processor core are provided. In one example, a computer-implemented method can comprise detecting, by a processor core, a voltage droop at a first area of the processor core. The computer-implemented method can also comprise transmitting, by the processor core, voltage droop information to a local controller located in the first area and to a global controller located in the processor core. Further, the computer-implemented method can comprise applying, by the processor core, a first mitigation countermeasure at the first area of the processor core in response to a local instruction received from the local controller. The local instruction can comprise an indication of the first mitigation countermeasure.

Abstract: A controller in a solid state luminaire implements a nested control loop to drive multiple, parallel-connected, heterogeneous strings of series-connected LEDs using a constant current power supply. The current through each string is independently controlled by a current regulator in series with the LEDs. An inner (current) control loop alters the relative drive strength of each LED string, to achieve desired luminous characteristics, such as CRI, CCT, and the like. An outer (voltage) control loop monitors the output voltage of the power supply, and the total current drawn. The outer control loop adjusts a gain factor applied to the control signals for each current regulator, to control the total current drawn—while maintaining the relative ratios of drive strength between the strings—so as to maintain the power supply output voltage at a substantially constant value.

Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.

Abstract: An LED device comprises a substrate and a stack of layers defining an LED component and including an electroluminescent layer. A capacitive structure is formed on top of the stack of layers. The area of the defined capacitor encodes information concerning the electrical characteristics of the LED component.

Abstract: A Josephson AND/OR gate circuit makes efficient use of Josephson junction (JJ) and inductor components to provide two-input, two-output AND/OR logical functions. The circuit includes four logical input storage loops that each contain one of two logical decision JJs that are configured such that they trigger to provide the OR and AND signals, respectively. Functional asymmetry is provided in the topologically symmetrical AND/OR gate circuit by a bias storage loop that includes both of the logical decision JJs and that is initialized to store a directional ?0 of current at system start-up.

Abstract: A parallel connectable light control system has a first driver and a second driver. A dimming control interface in the first driver. The dimming control interface has a sensor side signal and the dimming signal internal output. The dimming signal internal output outputs to a dimming signal external output. The sensor side signal outputs to a sensor side signal output. The second driver receives the dimming signal external output into a dimming control interface of the second driver.

Abstract: A system of unipolar digital logic. Ferroelectric field effect transistors having channels of a first polarity, are combined, in circuits, with simple field effect transistors having channels of the same polarity, to form logic gates and/or memory cells.

Abstract: A control circuit includes a first control unit, a power unit, a driver unit, a second control unit, a power source, a first switch, a pull-up element and a second switch. The first control unit is used to detect whether a configuration channel line has a predetermined divided voltage and generate a control signal accordingly. The power unit is coupled to the configuration channel line and a power line for supplying power to the driver unit. The driver unit is used to enable or disable a light emitting unit according to the control signal. The second control unit is used to detect whether the configuration channel line has the predetermined divided voltage and control the first switch and the second switch accordingly. The first switch is coupled between a power source and the configuration channel line. The second switch is coupled between the pull-up element and the configuration channel line.

Abstract: An inverting reciprocal quantum logic (RQL) gate circuit has an input stage having a logical input asserted based on receiving a positive single flux quantum (SFQ) pulse and an output stage comprising phase mode logic (PML) inverter circuitry. The input stage includes one or more storage loops, at least one being associated with each logical input, each comprising an input Josephson junction (JJ), a storage inductor, and a logical decision JJ, the logical decision JJ being common to all the storage loops associated with the logical inputs and being configured to trigger based on biasing provided by one or more currents stored in the storage loops and a first bias signal provided to the input stage. The output stage de-asserts an output and is provided with a second bias signal having a second state opposite of a first state of the first bias signal.

Abstract: Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a programmable logic device (PLD) includes a plurality of programmable logic blocks (PLBs) and at least first and second logic cells within at least one of the PLBs, where each logic cell includes a lookup table (LUT) and associated mode logic configured to receive a LUT output signal from the LUT. The associated mode logic is configured to use a single physical signal output to provide a logic cell output signal corresponding to a selected logic function operational mode, ripple arithmetic operational mode, or extended logic function operational mode for each logic cell.

Abstract: A lighting controller and a control method make use of a fade time over which the light source is to be controlled when adjusting the light source output from a first dimming level to a second dimming level. The fade time is selected in dependence on both the difference between the first and second dimming values and the absolute values of the first and second dimming levels. This enables smooth fading over a long time when desired for a high quality fading with no flicker, or rapid fading between brightness levels when the speed of response is more important.