Patents Examined by Don Phu Le
  • Patent number: 6480032
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: November 12, 2002
    Assignee: Intel Corporation
    Inventor: Randy J. Aksamit
  • Patent number: 6480020
    Abstract: A printed circuit board assembly (PCBA) includes first and second integrated-circuit terminals and first and second connector terminals. A first transmission line transmits a data signal and a second transmission line transmits a clocking signal. The PCBA includes integrated circuitry comprising first and second pads, a first digital circuit for propagating the data signal through the first pad and a second digital circuit for propagating the clocking signal through the second pad. The first transmission line includes a first integrated-circuit conductive path including a first series-connected integrated circuit resistive element and a first printed-circuit conductive path. The second transmission line includes a second integrated-circuit conductive path including a second integrated-circuit resistive element and a second printed-circuit conductive path.
    Type: Grant
    Filed: May 18, 1999
    Date of Patent: November 12, 2002
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hoover K. Jung, Sanjay S. Mathur, Virgil V. Wilkins
  • Patent number: 6480027
    Abstract: Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connection. Instances of the generalized driver module may be included anywhere on the programmable logic device that driver circuitry having characteristics within the capabilities of the generalized module is needed. The circuitry of each instance of the module is hardware-customized to match the driver characteristics required for that instance. Driver circuits may be distributed throughout the interconnection conductor resources of the programmable logic device in such a way as to optimize re-buffering of signals propagating through those resources.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: November 12, 2002
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Sergey Shumarayev, Wei-Jen Huang
  • Patent number: 6480026
    Abstract: A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 12, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: William B. Andrews, Harold N. Scholz
  • Patent number: 6476638
    Abstract: An input driver circuit for accommodating a plurality of input/output voltage standards is provided. The input driver circuit employs an adjustable trip point that can be calibrated for multiple input voltage standards. The adjustable trip point is provided by a trigger circuit. A control circuit determines whether the trigger circuit is on or off by comparing a configuration input thereof with a reference power supply input thereof. When the trigger circuit is on, the trip point is active during a low to high transition of the signal input.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: November 5, 2002
    Assignee: Xilinx, Inc.
    Inventors: Shi dong Zhou, Gubo Huang
  • Patent number: 6472906
    Abstract: An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: October 29, 2002
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Ikuo Jimmy Sanwo, Mahyar Nejat, Jean-Robert Clerge
  • Patent number: 6472904
    Abstract: A multi-functional programmable I/O buffer in a Field Programmable Gate Array (FPGA) device. The I/O buffer is programmably configurable to meet any of a wide range of I/O standards, be it single ended or differential, 5V, 3.3V, 2.5V or 1.5V logic, without the need for implementing multiple I/O buffers to properly handle each different iteration of I/O requirements. An embedded, internal programmable resistor (e.g., a programmable 100 ohm resistor) is programmably selected for use in differential I/O applications, thus eliminating the conventional requirement for the use of an external resistor connected to each differential receiver I/O pin. The present invention also separates I/O pads into groups in each of a plurality of banks in a programmable device (e.g., PLD, FPGA, etc.), with each group being separately powered by the user. The disclosed multi-functional I/O buffer may be programmably configured by the user to be, e.g.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: October 29, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: William B. Andrews, Barry K. Britton
  • Patent number: 6469541
    Abstract: A digital circuit configured to receive three or more input signals and produce an output signal corresponding to either an XOR or XNOR of the input signals. In one embodiment of the invention, the circuit includes a first section connected in series with a second section to form a three-input XOR or XNOR gate. The first section is a two-input XOR or XNOR circuit having no more than eight transistors, including two transmission gate pairs. The second section is a two-input XOR or XNOR circuit having no more than six transistors, including one transmission gate pair.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: October 22, 2002
    Assignee: Translogic Technology, Inc.
    Inventors: Dzung Joseph Tran, Mark W. Acuff
  • Patent number: 6466055
    Abstract: An integrated circuit input buffer system includes numerous buffers used to receive input signals. The buffer system controls the buffers in a manner that places some of the buffers in a standby mode while other buffers are active. The integrated circuit input buffer system reduces the capacitive load on any individual buffer. The buffers can be activated in a variety of patters, such as sequential activation. In one embodiment, the buffers have differential transistors coupled to receive differential input signals. The differential transistors are coupled to conduct a total current defined by a tail current circuit. The buffers are placed in a standby state by electrically isolating the tail current from the differential transistors. In one embodiment, a standby transistor is electrically located between the differential transistors and a tail current transistor. The differential transistors conduct a trickle current during the standby state.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: October 15, 2002
    Assignee: Xilinx, Inc.
    Inventor: Michael Joseph Gaboury
  • Patent number: 6462583
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: October 8, 2002
    Assignee: Intle Corporation
    Inventor: Randy J. Aksamit
  • Patent number: 6462580
    Abstract: The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: October 8, 2002
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
  • Patent number: 6459297
    Abstract: A system for programming field programmable devices (FPDs) of different types across different boards. An in-system programmable master (ISPM) communicates over a bus to in-system programmable slaves (ISPSs) on one or more boards. FPDs on each board are connected into chains of the same type, and each chain is connected to an ISPS located on the board. The ISPM uses a packet protocol to communicate with all ISPSs in a system. Each packet comprises an ISPS address field, a chain select field, and a command field. Each ISPS reads packets addressed to it, and decodes and transmits the commands to the selected FPD chain in a protocol appropriate to the chain.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: October 1, 2002
    Assignee: AG Communication Systems Corporation
    Inventor: David A. Smiley
  • Patent number: 6459304
    Abstract: The present invention provides a precharge circuit that has a first precharged node, a second precharged node, and a latch device. The first precharged node is charged to a high value during a precharge state. In response to a transition from the precharge state to an evaluate state, it either discharges to a low value or remains charged at its high value. The second precharged node has a value in the evaluate state that is based on the value of the first precharged node upon the circuit transitioning to the evaluate state. The latch device is connected to the second precharged node for latching this value in the evaluate state. With the latching device, this value is not affected by the first precharged node once the circuit has sufficiently transitioned to the evaluate state.
    Type: Grant
    Filed: February 21, 2000
    Date of Patent: October 1, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Samuel D Naffziger, Jayen J Desai, Reid James Riedlinger
  • Patent number: 6459302
    Abstract: A D-FF circuit comprises: a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit; wherein the slave flip-flop comprises: a clocked inverter which is disposed on a first stage of the slave flip-flop and which operates in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and a two-stage inverter which is connected in series with an output terminal of the clocked inverter.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: October 1, 2002
    Assignee: Ando Electric Co., Ltd.
    Inventor: Kazuo Nakaizumi
  • Patent number: 6456119
    Abstract: A decoding apparatus for transmitting a high voltage signal includes a final decoder for switchably transmitting a transmission signal. The final decoder has a switching device that has at least one depletion-mode-type field effect transistor and/or field effect transistor having a low threshold voltage (i.e., 0.1 to 0.4 V), in particular, a low VT field effect transistor. A transmission signal line supplies the transmission signal to the decoder, a driver signal line supplies a driver signal to the decoder, and an output signal line outputs an output signal from the decoder. The driver signal line applies the driver signal to the gate line, the transmission signal line applies the transmission signal to the source line. The field effect transistor is configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal. The configuration reduces the likelihood of channel degradation and of failure in the field effect transistor.
    Type: Grant
    Filed: February 20, 2001
    Date of Patent: September 24, 2002
    Assignee: Infineon Technologies AG
    Inventor: Helmut Fischer
  • Patent number: 6456113
    Abstract: A slave latch circuit has a gate for being supplied with a signal which is an inversion of a signal outputted from a first output terminal and a control'signal, generating a signal based on the supplied signals, and outputting the generated signal from a second output terminal. The gate controls the output signal outputted from the second output terminal. The gate may comprise a NAND gate for being supplied with a ground potential as the control signal in a normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a power supply potential. Alternatively, the gate may comprise a NOR gate for being supplied with the power supply potential as the control signal in the normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a ground potential.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: September 24, 2002
    Assignee: NEC Corporation
    Inventor: Kohji Kanba
  • Patent number: 6456109
    Abstract: A jitter detecting circuit firstly compares a target signal with a reference clock signal to see whether or not a phase difference takes place between the target signal and the reference clock signal, and, thereafter, the phase difference in each clock cycle is compared with the phase difference in the previous clock cycle for producing a detecting signal representative of cycle-to-cycle jitter when the phase difference is varied.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: September 24, 2002
    Assignee: NEC Corporation
    Inventor: Kenji Urushiyama
  • Patent number: 6456107
    Abstract: A method for regulating resonance in a micro-chip has been developed. The circuit includes an on-chip de-coupled capacitor that is shunted across the supply and ground voltages, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: September 24, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Tyler J. Thorp, Richard L. Wheeler, Brian Amick
  • Patent number: 6452418
    Abstract: A driving circuit provides a symmetric differential driving signal relative to one set of voltage potentials to a driver circuit that drives an output node to another set of voltage potentials. The differential driving signals from the driving system are equal and opposite to each other, thereby avoiding stray current flow between the driving system and the driven current mirrors. The transistors that provide the driving signal are continuously biased, using a weak bias in one logic state and stronger bias in the other state, to avoid hard-switching transients.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: September 17, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Balwinder Singh, Klaas-Jan De Langen, Martijn Bredius
  • Patent number: 6452421
    Abstract: A source synchronous type interface circuit in which, for fetch of a transmitted data, a source synchronous clock indicating a data transmission timing is transmitted from transmission to reception side along with the data, so that a reception clock is generated to define an operation timing of a first reception flip-flop for taking in a data from the reception signal of the source synchronous clock. The interface further includes a second reception flip-flop for feeding an output from the first reception flip-flop further to a second reception flip-flop in synchronization with a common system clock and a variable delay circuit for absorbing phase fluctuations of the first reception flip-flop depending on transmission delay time, to assure a phase difference required for correctly receiving the data. The variable delay circuit has a delay amount automatically controlled according to phase differences between the system clock and the source synchronous clock received.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: September 17, 2002
    Assignee: Hitachi, Ltd.
    Inventor: Tatsuya Saito