Abstract: In a cellular-telephone-system base-station receiver's channelizer (111), frequency translation of the outputs of a filter bank (FIG. 5) implemented in fast-Fourier-transform circuitry (453,455,460) is achieved by rotating the correspondence between FFT input elements and the filter coefficients by which multipliers (437) multiply incoming samples to produce them. Specifically, a storage-address generator (482) directs that corresponding FFT input elements of successive FFT operations be stored in the same locations in an input-data memory (451). To retrieve those values for use in the DFT operation, however, a fetch-address generator (484) employs a modulo-K adder (488) to impose a changing offset so that the starting address for retrieval of each FFT operation's input record changes between FFT operations by the filter bank's decimation rate M.

Abstract: A cellular telephone system having three or more cell sites with each cell site having a source of cellular communication signals and an RF transmitter and antenna for broadcasting the cellular communication signals. A direct sequence spread spectrum waveform carrying navigation signals is embedded in the cellular communication signals, including controlling the signal strength of the navigation signals so that the combined energy of the navigation signals from all cell sites at any location is at least a predetermined energy level below the energy level of the cellular communication signals. Each cell site includes timing for timing the operation of a GPS receiver.

Abstract: A bidirectional radio system for low-cost high-throughput accumulation of data from a large number of site units. Frequency synchronization is achieved at low cost by transmitting a high accuracy carrier and clock signal at a base station, and using receiving circuitry at remote stations to extract the base clock signal and base carrier frequency and a phase-lock loop to stabilize the remote station carriers. A burst demodulator at a base station receiver can decode a short remote station response by scaling the response with the phase and amplitude of an initial segment of the response. The burst demodulator may continuously update the decoding threshold based on a comparison of the signal amplitude and the current value of the decoding threshold. In an alternate embodiment, the carrier synthesizer is not part of a phase-lock loop, but the transmitted signal is rotated by a phase proportional to a frequency error to provide an accurate carrier frequency.

Abstract: In a quantization noise reduction circuit (200), a feedback signal (W)is added to an input signal (X) to the quantization circuit to reduce quantization noise. The feedback signal is generated as a filtered difference between a sample of a N bit signal (X') and a time coincident sample of a M bit quantized signal, where M<N. The feedback signal is subtracted from the input signal (X) prior to quantization thereby introducing out of band noise into the input signal for reducing in band noise in the quantized signal (Y).

Abstract: A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from 3/16 to 8/16 of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream.

Abstract: A system and method for the transmission and recovery of asynchronous data. For instantaneous synchronization, the receiver is equipped with a high frequency timing base which has a far higher frequency than either the data-generating or transmitting rate. The receiver clock is instantly synchronized upon detection of the first transition of the incoming data packet. Data packet verification can be conducted and data processed with minimal loss of data.

Abstract: A method and apparatus for recovering the phase of a symbol clock operating at a predetermined symbol rate is described. A modulated RF signal which has been downconverted or a modulated baseband signal is filtered and sampled by a high speed converter. A high speed digital signal processor processes the digitized signal to determine the phase of the symbol clock. The symbol phase is determined independent of carrier phase by repetitively resampling the digitized signal and constructing the histogram for each resample of that signal. By comparing the histograms of each resample the symbol phase may be identified. Using the symbol rate and phase, the signal may be analyzed for carrier phase and frequency errors and modulation accuracy using eye diagrams, modulation trajectories and symbol content.

Abstract: A system for creation of user-selected customized audio products, defined as a plurality of songs from different recording artists recorded on a single compact disc (CD) or digital audio tape (DAT) cassette, at record store/distributor locations utilizing a digitized, central database with production hardware at distributor sites. Customized products consist of CD ROM or digital audio tapes (DAT) with music or voice content selected from large digital database, and are written at local workstations at distribution centers (such as record stores) which are connected by a high-speed communications network. The system records costs of the digitized audio (e.g., royalties for individual songs) for billing purposes, as well as producing descriptive material (contents, background information, and graphics for labels, etc.).

Abstract: In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices.

Abstract: A transmitting equipment includes a holding circuit for dividing a time-series digital signal into I and Q digital signals, holding the I and Q digital signals, and outputting them in parallel, a waveform forming circuit, having a memory for storing a plurality of oversampling codes corresponding to the I and Q digital signals, for reading the oversampling codes out of the memory and outputting them as I and Q waveform forming signals, a modulation circuit for orthogonally modulating the I and Q waveform forming signals output from the waveform forming circuit and outputting I and Q modulated signals, an addition circuit for adding the I and Q modulated signals output from the modulation circuit and outputting I and Q sum signals, a filter for removing high-frequency components from the I and Q sum signals output from the addition circuit, and a transmitting signal generation circuit for adding the I and Q sum signals from which the high-frequency components are removed by the filter and generating a transmit

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: A coherent detection system synchronously detects a received wave involving a Doppler shift.

Abstract: Digital information is transmitted by generating coded signals in the form of pulses on the basis of binary digital information and decoding the coded signals into the binary digital information, the pulses being coded in the time domain and being of at least two distinctly different shapes with respect to their numerical amplitude variation along the time axis of the pulses, the pulses comprising two bits of information in each pulse having energy one, but coded in the way that one bit of information is in the polarity and one bit in the shape, or two bits are in the shape.

Abstract: An automatic frequency control apparatus includes a sampling portion for sampling the signal transmitted according to a phase-shift keying method, a phase difference detector for detecting the phase difference between the currently sampled signal and the immediately preceding sampled signal, and a phase bin comparator for determining which of a number of reference phases the phase of the transmitted signal is closest to, using a quantization characteristic of phase during transmission. The frequency offset generated by the distance between the frequency of a carrier wave and the local oscillation frequency of a receiver, or by the Doppler shift, in a MPSK communication method is determined as the phase difference between the detected phase difference information and the determined reference phase information. The apparatus can be used for the automatic frequency control of a modem using any type of MPSK modulation.

Abstract: A Viterbi equalizer can provide an accurate equalizing characteristic. This Viterbi equalizer comprises a synchronizing signal data detecting circuit for detecting a synchronizing signal data portion from a reception signal data series, a transmission line characteristic estimating circuit for modelling an impulse response between a transmitter and a receiver by comparing a synchronizing signal data detected by the synchronizing signal data detecting circuit with a reference signal, and a decoding circuit for decoding a transmission data series by using a Viterbi algorithm on the basis of a transmission model obtained from the transmission line characteristic estimating circuit.

Abstract: A bit error counter for a digital communication system has transmitter and receiver. The transmitter includes circuitry for convolution encoding of an input original signal and outputting a transmission signal. The receiver includes error correcting/decoding circuitry for inputting a reception signal corresponding to the transmission signal and outputting a decoded signal, and when an overflow occurs, for outputting an overflow signal. State monitoring circuitry is provided for receiving the overflow signal and issuing a switching instruction signal to a switch only when the overflow signal is received. The switch also receives the decoded signal and outputs at least one of a bit error rate or a number of errors when the switching instruction signal is received. The switch outputs the decoded signal when the switching instruction signal is not received.

Abstract: A dynamic clock mode switch (11) is provided for switching clock frequencies while allowing continuing operation of a depending system. The switch includes an enable circuit for transmitting an enable signal, a phase-locked loop circuit (PLL) (15) for locking onto an input clock frequency in response to said enable circuit, a PLL lock indicator for receiving a PLL lock signal (29) from said PLL, and a clock multiplexer with a multiplier for multiplying said input clock frequency by a predetermined factor in response to said enable circuit and PLL clock signals.

Abstract: A delay detection is performed to baseband signals subjected to an orthogonal demodulation to obtain a delay detection output and a frequency error is found from the delay detection output. The frequency error is converted into a control frequency which is accumulated to generate a phase rotation .phi. which is used to rotate the input baseband signals before being subjected to the delay detection, thereby to perform frequency correction. By providing filters downstream of a phase rotation circuit and upstream of a delay detection circuit, automatic frequency control can be realized without performance deterioration.

Abstract: A communication unit (103) transmits a concurrent monitoring request to a base station (102). Responsive to the concurrent monitoring request, the base station provides multiple communications from at least one dispatch position (101) and at least one other communication unit (104) to the communication unit. Upon reception of the multiple communications, the communication unit simultaneously renders the multiple communications audible, allowing an operator of the communication unit to concurrently monitor the multiple communications.

Abstract: A high-speed out-of-band signalling technique for transferring information such as station status information between stations in a communication network, typically a local-area network, involves sequentially generating a plurality of n-bit sequence segments, where n is at least 3. Each bit is either a first binary value or a second binary value. Each sequence segment is coded with one of a plurality of different n-bit code groups divided into a first code group and a set of second code groups. The n bits in the first code group are all the first binary value--e.g., all "1s". None of the second code groups contain a pair of non-contiguous bits of the second binary value--e.g., none of the second code groups contains two "0s" separated by at least one other bit. The sequence segments are outputted in the order that they were generated to produce a special bit sequence which carries the desired information.