Abstract: A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

Abstract: A device for forming an encapsulated end of a wire bonded to a metal surface. The device includes a clamp being an end surface of a bar is pressed against a surface of a plate. The end surface has a ridge formed around its edge. Therefore, when a clamping force is applied to the bar against the plate, the metal sheet clamped between the plate surface and end surface of the bar, the clamping force is concentrated at an interface between the metal surface and ridge. When encapsulate is injected into the contact region, the ridge prevents contaminating material from migrating over interface between bar and plate where the welding step is to be performed. The bar is then withdrawn leaving a tunnel through which the wire is positioned with the end of the wire in contact bondable to the clean surface of metal. The wire is positioned in the tunnel and bonded to the metal surface.

Abstract: A failure analyzing method using a failure-analyzing semiconductor device includes a first step of manufacturing a semiconductor device adapted for product in predetermined numbers during a first interval and a second step of manufacturing a failure-analyzing semiconductor device in predetermined numbers every second interval during the first interval. The first step includes a step of forming memory cells in a first semiconductor substrate. The second step includes a step of forming memory cells in a second semiconductor substrate and a step of forming first and second digitated interconnections at the same level above the second semiconductor substrate, which are connected to the memory cells and arranged so that the fingers of each of the first and second interconnections are interleaved with those of the other with a predetermined space therebetween.

Abstract: A buried Zener diode structure and method of manufacture requires no additional process steps beyond those required in a basic standard bipolar flow with up-down isolation. The buried Zener diode has its N++/P+ junction removed from the silicon surface.

Abstract: A semiconductor device is capable of ensuring bonding strength without applying an excessive stress to solder balls and has a high degree of reliability. The semiconductor device includes a substrate made of metal, the substrate having a central portion with a hollow region and a peripheral portion that surrounds the central portion. The central portion of the substrate has a through hole. The semiconductor device also includes a semiconductor chip that is mounted on the central portion of the substrate, and solder balls that are carried on the peripheral portion.

Abstract: A layout structure of column pass transistors of a semiconductor memory device, in which the area occupied with the transistors is reduced. Thus, in spite of high integration of the semiconductor memory device and miniaturization of memory cells, column path transistors can be arranged efficiently. In the aforementioned layout structure, the active regions of the column path transistors are longitudinally in perpendicular to the bit line pairs to reduce the area occupied with the total number of memory cells.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: An electrostatic discharge protection device is provided at an input or output of a semiconductor integrated circuit for protecting an internal circuit from an electrostatic surge flowing into or out of the integrated circuit. The electrostatic discharge protection device may include a thyristor, and a trigger diode for triggering the thyristor (e.g., with a low voltage). The trigger diode may include an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the cathode region from another silicide layer formed on a surface of the anode region.

Abstract: FLASH memory circuitry includes an array area and peripheral circuitry area. Multiple series of spaced isolation trenches are provided. At least one of the series of spaced trench isolation regions is formed in a semiconductor substrate within the FLASH peripheral circuitry area. At least some of the FLASH peripheral circuitry area spaced trench isolation regions have maximum depths which are greater than first and second maximum depths of trench isolation regions formed within array area.

Abstract: The electronic component has semiconductor chips that are stacked on one another. On their active top sides, the chips having interconnects for rewiring to contact areas through contacts formed on the sawn edges of the semiconductor chip. The electronic components of overlying and underlying semiconductor chips are thus connected to one another via the through contacts.

Abstract: Structures and methods for making a magnetic structure are discussed. Various embodiments increase a magnetic field to unambiguously select a magnetic memory cell structure. One method includes folding a current line into two portions around a magnetic memory cell structure. Each portion contributes its magnetic flux to increase the magnetic field to unambiguously select the magnetic memory cell structure. Another method increases the flux density by reducing a cross-sectional area of a portion of the current line, wherein the portion of the current line is adjacent to the to the magnetic memory cell structure.

Abstract: An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.

Abstract: A device and method for increasing input/output from a die by making electrically conductive microvias connecting the integrated circuit with a backside of the die. The backside electrically conductive microvias connect an integrated circuit in the die to pads on the backside of the die. A superstrate is situated on top of the die and connects to the microvias using controlled collapse chip connections (C4) with a thermal interface material (TIM) surrounding the electrical connections. A superstrate lead system electrically connects the backside pads to wirebonds that connect with either the substrate or directly to the motherboard. Heat dissipates from the die via the TIM to the superstrate to a heat sink situated on top of the superstate.

Abstract: The dual-bit flash memory cells of the present invention include three regions: the gate region, the first-side region, and the second-side region. The gate region is formed between the first-side region and the second-side region and is defined by a masking photoresist step and is scalable. The gate region includes two stack-gate transistors formed in the side portions of the gate region with a select-gate transistor being formed therebetween for the first embodiment of the present invention and with a bit-line conductive island formed over a common-drain diffusion region for the second embodiment of the present invention. The first-side/second-side region includes a common-source conductive bus line being integrated with a conductive erasing anode for high-speed erasing. The cell size of each bit is smaller than 4F2.

Abstract: A protective circuit in a semiconductor device includes a protective n-channel MOS transistor connected between the power source line and the ground line, with the gate and drain being connected together, and an n-p-n transistor having a base connected to the source of the protective n-channel MOS transistor and connected between the power source line and the ground line. The protective circuit disposed in a low-voltage semiconductor device has a lower power dissipation due to a low junction leakage current.

Abstract: An apparatus for fabricating encapsulated micro-channels in a substrate is described. The apparatus includes the formation of a thin film layer over an area of a substrate. Following the formation of the thin layer, a periodic array of access windows are formed within the thin film layer along dimensions of one or more desired micro-channels. Following formation of the access windows, the one or more micro-channels are formed within an underlying layer of the substrate. Finally, the one or more micro-channels are encapsulated, thereby closing the one or more access windows along the dimensions of the desired micro-channels. Accordingly, the apparatus is suitable in one context for rapid prototyping of micro-electromechanical systems in the areas of, for example, RF micro-systems, fluidic micro-systems and bio-fluidic applications. In addition, the apparatus enables the rapid prototyping of integrated circuits.

Abstract: A vertical power transistor trench-gate semiconductor device has an active area (100) accommodating transistor cells and an inactive area (200) accommodating a gate electrode (25) (FIG. 6). While an n-type layer (14) suitable for drain regions still extends to the semiconductor body surface (10a), gate material (11) is deposited in silicon dioxide insulated (17) trenches (20) and planarised to the top of the trenches (20) in the active (100) and inactive (200) areas. Implantation steps then provide p-type channel-accommodating body regions (15A) in the active area (100) and p-type regions (15B) in the inactive area (200), and then source regions (13) in the active area (100). Further gate material (111) is then provided extending from the gate material (11) in the inactive area (200) and onto a top surface insulating layer (17B) for contact with the gate electrode (25).

Abstract: An LED with improved current spreading structures that provide enhanced current injection into the LED's active layer, improving its power and luminous flux. The current spreading structures can be used in LEDs larger than conventional LEDs while maintaining the enhanced current injection. The invention is particularly applicable to LEDs having insulating substrates but can also reduce the series resistance of LEDs having conductive substrates. The improved structures comprise conductive fingers that form cooperating conductive paths that ensure that current spreads from the p-type and n-type contacts into the fingers and uniformly spreads though the oppositely doped layers. The current then spreads to the active layer to uniformly inject electrons and holes throughout the active layer, which recombine to emit light.

Abstract: Image sensors with an enhanced QE and MTF in the NIR spectral region are fabricated on the standard substrates. This is achieved by replacing the p+ type doped layer, typically present under the thick field oxide in the inactive regions of the sensor, with an n+ type doped layer. The n+ type layer, which is biased at the Vdd potential, surrounds the entire image sensor array as a guard ring and is separated from the CCD or CMOS array pixels by a suitable potential barrier. The potential barrier prevents collected charge from escaping into the n+ layer regions. Additional embodiments include output diode and MOS transistor designs that use field plates for creating potential barriers that separate these devices from the n+ type doped field regions.

Abstract: All source regions belonging to a row are electrically connected to one another through a silicon layer (4) in a portion between a bottom surface of a partial-isolation insulating film (5) and an upper surface of a BOX layer (3). These constitute source lines (SL1 to SL5) extending like strips in a row direction. The isolation insulating film (5) between the source regions adjacent to each other in the row direction is removed and in the silicon layer (4) of the portion exposed by removing the isolation insulating film (5), an impurity introduction region (10) having the same conductivity type as the source region has is formed. With this structure, a nonvolatile semiconductor memory device which causes no malfunction due to driving of a parasitic bipolar transistor can be provided.