Patents Examined by Douglas M Menz
  • Patent number: 10483156
    Abstract: A method includes electrically joining two or more semiconductor chips to a silicon bridge chip, and electrically joining the two or more semiconductor chips to a substrate structure, the silicon bridge chip extends into a recess in the substrate structure such that a top surface of the silicon bridge chip is substantially flush with a top surface of the substrate structure.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10472735
    Abstract: There is herein described a method of making a single crystal wavelength conversion element from a polycrystalline wavelength conversion element, a single crystal wavelength conversion element, and a light source containing same. By making the single crystal wavelength conversion element from a polycrystalline wavelength conversion element, the method provides greater flexibility in creating single crystal wavelength conversion elements as compared to melt grown methods for forming single crystals. Advantages may include higher activator contents, forming more complex shapes without machining, providing a wider range of possible activator gradients and higher growth rates at lower temperatures.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: November 12, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: John Kelso, Alan Piquette, David Johnston
  • Patent number: 10461049
    Abstract: An aluminum electrode (2) is provided on a semiconductor device (1). A metallic film (3) for a solder joint is provided on the aluminum electrode (2). The organic protective film (4) is apart from the metallic film (3). An interval between the organic protective film (4) and the metallic film (3) is equal to or greater than half of a thickness of the organic protective film (4). Thus, even when the organic protective film (4) is deformed during sinter joining, the stress is not transmitted to the metallic film (3). Therefore, it is possible to prevent the solder connection metallic film (3) from cracking.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: October 29, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Hamaguchi, Yosuke Nakata, Seiya Nakano, Masayoshi Tarutani
  • Patent number: 10461025
    Abstract: A method for metallization during fabrication of an Integrated Circuit (IC). The IC includes a semiconductor wafer having a back surface and a front surface. The method includes etching a via hole through the semiconductor wafer. After this, a seed metal layer is deposited on the back surface of the semiconductor wafer. Thereafter, a photoresist layer is deposited on the back surface of the semiconductor wafer such that the via hole remains uncovered. After depositing the photoresist layer, a metal layer is formed along the walls of the via hole to electrically connect the back surface and the front surface of the semiconductor wafer. Finally, the photoresist layer is removed subsequent to forming the metal layer.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 29, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Mohsen Shokrani, Boris Gedzberg, Ronald Michels
  • Patent number: 10454058
    Abstract: An organic light emitting diode display device includes a substrate. A first protective layer is disposed on the substrate. A conductive line is disposed on the first protective layer. A second protective layer is disposed on the conductive line. A first electrode is disposed on the second protective layer. An organic light emitting layer is disposed on the first electrode. A second electrode is disposed on the light emitting layer. The first electrode is symmetric with respect to a center of the conductive line.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Moojong Kim
  • Patent number: 10453901
    Abstract: A display device and a method of manufacturing the display device are provided. A display device includes: a plurality of first emission areas and a plurality of second emission areas alternately arranged at centers of virtual quadrangles aligned adjacent to each other in a row direction and a column direction; and a plurality of third areas respectively arranged at vertexes of the virtual quadrangles, and a difference between planar areas of the first to third emission areas is less than 25% of a largest planar area among the planar areas of the first to third emission areas.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 22, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunwoong Kim, Seungkyu Lee, Wonkyu Kwak, Jongwon Park
  • Patent number: 10444586
    Abstract: A liquid crystal display (LCD) device capable of perventing impurities from permeating into a channel area of a switching element, the LCD device including: a gate electrode above a substrate; a semiconductor layer which overlaps the gate electrode; a drain electrode and a source electrode which overlap the semiconductor layer; an ohmic contact layer between the semiconductor layer and the drain electrode and between the semiconductor layer and the source electrode; a pixel electrode which is connected to one of the drain electrode and the source electrode; and a gate insulating layer between the gate electrode and the semiconductor layer, the gate insulating layer comprising fluorine. A concentration of the fluorine is decreasing, as the fluorine of the gate insulating layer being more adjacent to the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Taeyoung Ahn, Bogeon Jeon, Wooseok Jeon, Yungbin Chung, Eunjeong Cho
  • Patent number: 10446789
    Abstract: A display device and a method of manufacturing a display device are provided. A display device includes a substrate; a display area on the substrate and configured to display an image; a pad portion on at least one edge of the substrate, the pad portion including at least one sink portion; an anisotropic conductive film on the pad portion and filling the at least one sink portion, the anisotropic conductive film spaced apart from an end of the substrate; and a flexible printed circuit board on the anisotropic conductive film and electrically connected to the pad portion.
    Type: Grant
    Filed: February 16, 2019
    Date of Patent: October 15, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Eunah Kim, Miae Kim
  • Patent number: 10438160
    Abstract: Repurpose Intelligence System for repurposing expired food stuffs and ensuring that locked-up nutrients in these expired food stuffs find their way into the supply chain so that their values is realized.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: October 8, 2019
    Inventors: John New, Michael Dershem
  • Patent number: 10431676
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a first III-V group compound semiconductor layer disposed on the substrate. The first III-V group compound semiconductor layer includes a fin structure having a top surface, a first sidewall, and a second sidewall opposite to the first sidewall. The semiconductor device also includes a second III-V group compound semiconductor layer disposed on the first III-V group compound semiconductor layer. The first III-V group compound semiconductor layer and the second III-V group compound semiconductor layer are made of different materials. The semiconductor device also includes a gate electrode disposed on the second III-V group compound semiconductor layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 1, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Yu-Chieh Chou
  • Patent number: 10424579
    Abstract: A semiconductor device for electric discharge protection is disclosed. In one aspect, the semiconductor device includes a substrate having a p-type doping. The semiconductor device includes a first well and a second well having an n-type doping and arranged spaced apart within a surface layer of the substrate, and a third well having a p-type doping and arranged in the surface layer of the substrate between the first well and the second well. The semiconductor device further includes an emitter region and a base contact region having a p-type doping and arranged within a surface layer of the first well, and a collector region having a p-type doping. The collector region is arranged at least partly within a surface layer of the third well and such that it overlaps both of the first well and the second well. An integrated circuit including a semiconductor device is also provided.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 24, 2019
    Assignee: IMEC vzw
    Inventors: Mirko Scholz, Shih-Hung Chen
  • Patent number: 10418406
    Abstract: Aspects and examples described herein provide a hybrid imaging sensor chip assembly for reducing undesired radiative transfer between a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC) and an optical detector, and methods of manufacturing a hybrid imaging sensor chip assembly. In one example, a hybrid imaging sensor chip assembly includes an optical detector configured to collect electromagnetic radiation incident thereon, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit (ROIC), and a radiation-shielding wafer interposed between the optical detector and the CMOS ROIC, the radiation-shielding wafer including a plurality of through wafer vias (TWVs) electrically coupled to the optical detector and the CMOS ROIC, the radiation-shielding wafer being positioned to prevent radiative transfer between the CMOS ROIC and the optical detector.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 17, 2019
    Assignee: RAYTHEON COMPANY
    Inventors: Sean P. Kilcoyne, John L. Vampola, Barry M. Starr, Chad W. Fulk, Christopher L. Mears, John J. Drab
  • Patent number: 10418468
    Abstract: The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (HBTs) that have different emitter ballast resistances. The disclosed semiconductor device includes a substrate, a first HBT and a second HBT formed over the substrate. The first HBT includes a first collector, a first base over the first collector, a first emitter over the first base, and a first cap structure over the first emitter. The second HBT includes a second collector, a second base over the second collector, a second emitter over the second base, and a second cap structure over the second emitter. Herein, the first cap structure is different from the second cap structure, such that a first emitter ballast resistance from the first cap structure is at least 1.5 times greater than a second emitter ballast resistance from the second cap structure.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: September 17, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian G. Moser, Thomas James Rogers
  • Patent number: 10411219
    Abstract: A display device and a method of manufacturing a display device are provided. A manufacturing method of a display apparatus includes forming a display module including a first area and including a display panel including lower and upper surfaces opposite each other, a first film under the lower surface of the display panel, a second film on the upper surface of the display panel, and an adhesive layer between the lower surface of the display panel and the first film; weakening an adhesive force of a first adhesive portion of the adhesive layer in the first area to be weaker than an adhesive force of a second adhesive portion of the adhesive layer outside the first area; cutting the first film and the adhesive layer; and removing a portion of the first film and the first adhesive portion from the first area.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 10, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Taehyun Sung, Kwan-su Kim, Junghoon Han, Kyoungil Min, Hyungu Lee, Junshik Park
  • Patent number: 10403685
    Abstract: A display device includes a substrate having a plurality of transmissive regions aligned in a first direction and a second direction, a plurality of first wiring lines on the substrate extending in the first direction, a plurality of second wiring lines on the substrate extending in the second direction, and a plurality of light emitting sections disposed on the substrate. Each of the transmissive regions is surrounded by the first and second wiring lines. The light emitting sections include a first light emitting section and a second light emitting section. At least part of the first light emitting section is located in a region that is adjacent to the transmissive regions and overlap one of the first wiring lines. At least part of the second light emitting section is located in a region that is adjacent to the transmissive regions and overlap one of the second wiring lines.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: September 3, 2019
    Assignee: Japan Display Inc.
    Inventor: Toshihiro Sato
  • Patent number: 10403705
    Abstract: Disclosed are an organic light emitting display device capable of achieving an intra-pixel integration design with sufficient storage capacitance and a method for manufacturing the same in which the organic light emitting display device includes a first active layer connected to the driving gate electrode and the data line while crossing the gate line, and a second active layer spaced apart from the first active layer while overlapping the driving gate electrode and being connected to the current drive line and storage electrode.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: September 3, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kum-Mi Oh, Hye-Seon Eom, Shun-Young Yang, Jeoung-In Lee
  • Patent number: 10388716
    Abstract: An organic light-emitting apparatus includes a substrate including an active area, a dead area, and a pad area, a display unit disposed in the active area and including thin-film transistors, pixel electrodes, and a portion of a common electrode, a first voltage supply unit disposed on the dead and pad areas and electrically contacting the common electrode, a second voltage supply unit overlapping the common electrode, and spaced apart and electrically insulated therefrom, and an insulating layer disposed between the common electrode and the second voltage supply unit, in which a portion of the common electrode that overlaps the first voltage supply unit is closer to the pad area than that of a portion of the common electrode that overlaps the second voltage supply unit, and an end portion of the insulating layer contacts an end portion of the first voltage supply unit adjacent to the active area.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyejin Shin
  • Patent number: 10379527
    Abstract: Techniques for automatically testing an entire process control loop, such as after components and portions of the loop have been commissioned separately, or after run-time operation begins, enable the process control loop to be tested without an operator in a back-end environment of a process plant coordinating with an operator in a field environment of the process plant to supply inputs and/or generate various conditions at the loop. Instead, a single operator performs a single operation to initiate an automatic loop test, or in some implementations, no user input is needed to initiate and/or perform the automatic loop test. Automatic loop testing includes automatically causing a field device to operate in a plurality of test states and determining whether resultant loop behaviors are expected behaviors. Multiple loops may be tested concurrently or distinct in time. An automatic loop test result is generated and may be presented via a user interface.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 13, 2019
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC.
    Inventors: Larry O. Jundt, Sergio Diaz, Julian K. Naidoo, Daniel R. Strinden, Cristopher Ian S. Uy, Gary K. Law, Neil J. Peterson, Kent A. Burr, Deborah R. Colclazier
  • Patent number: 10373957
    Abstract: A capacitor structure includes a semiconductor substrate, a dielectric layer disposed on the semiconductor substrate, a storage node pad disposed in the dielectric layer, and a cylindrical lower electrode including a bottom portion recessed into the dielectric layer and in contact with the storage node pad. The bottom extends to a sidewall of the storage node pad.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Wang Zhan, Chieh-Te Chen
  • Patent number: 10359745
    Abstract: Devices, systems, and methods for building system commissioning automation are described herein. One device includes a controller of a plurality of building system devices having logic to receive a set of commands specified by a sequence of operations (SOO) script, execute the set of commands to run an SOO check on the plurality of building system devices, and generate a report including results of the SOO check.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: July 23, 2019
    Assignee: Honeywell International Inc.
    Inventors: Jayaprakash Meruva, Manish Gupta, Andrew David Halford, Cary Leen, Roy Alan Kolasa