Abstract: A semiconductor structure includes a first substrate including a first contact structure located on a first pad, and a second substrate including a second contact structure on a second pad. The first contact structure includes a first metal base layer covered by a first nano-twinned metal coating layer. The second contact structure includes a second nano-twinned metal coating layer on the second pad. The first contact structure is connected to the second contact structure, thereby forming a bonding interface between the first nano-twinned metal coating layer and the second nano-twinned metal coating layer.
Abstract: A diaphragm-based sensor includes a deflectable diaphragm, a base layer opposite the diaphragm, and a corrugated wall extending between the diaphragm and the base layer. The diaphragm is suspended over a cavity enclosed by the diaphragm, the base layer and the corrugated wall. The diaphragm includes a first electrode and the base layer includes a second electrode such that a capacitance between the first and second electrodes changes when the diaphragm is deflected relative to the cavity.
Abstract: A piezoelectric micromachined ultrasonic transducer (PMUT) includes a substrate, a stopper, and a membrane, where the substrate and the stopper are composed of same single-crystalline material. The substrate has a cavity penetrating the substrate, and the stopper protrudes from a top surface of the substrate and surrounds the edge of the cavity. The membrane is disposed over the cavity and attached to the stopper.
May 21, 2020
Date of Patent:
November 15, 2022
Vanguard International Semiconductor Corporation
Abstract: A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.
March 3, 2021
Date of Patent:
November 15, 2022
NXP USA, INC.
Burton Jesse Carpenter, Fred T. Brauchler
Abstract: An image sensor includes a substrate having a first surface and a second surface facing each other, a plurality of photoelectric conversion regions disposed in the substrate, an isolation pattern disposed in the substrate between the photoelectric conversion regions, a conductive connection pattern disposed on the isolation pattern and in a trench penetrating the first surface of the substrate, and a first impurity region disposed in the substrate and adjacent to the first surface of the substrate. A first sidewall of the conductive connection pattern is in contact with the first impurity region. A dopant included in the conductive connection pattern includes the same element as an impurity doped in the first impurity region.
Abstract: An active matrix substrate includes a pixel region including a plurality of pixels over a substrate and a frame region outside the pixel region. In the plurality of pixels, a plurality of photoelectric conversion elements are provided. In the frame region, an antistatic hole is provided. The pixel region and a portion of the frame region are covered with an insulating film, and the antistatic hole is bored through the insulating film. An antistatic wire is provided in the frame region so as to surround the pixel region, and has a surface exposed in the antistatic hole.
Abstract: A conductive structure is provided. The conductive structure includes a first conductive layer, a second conductive layer, and an insulating layer sandwiched between the first conductive layer and second conductive layer. The insulating layer has a first opening and a second opening through which the first conductive layer is electrically connected to the second conductive layer. The partition between the first opening and the second opening has a width greater than 0 and less than or equal to the average width of the first opening and second opening.
Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.
Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.
Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.
Abstract: A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern.
September 23, 2020
Date of Patent:
October 11, 2022
Seong-Min Son, Jeong-Gi Jin, Jin-Ho An, Jin-Ho Chun, Kwang-Jin Moon, Ho-Jin Lee
Abstract: A semiconductor device may include a semiconductor substrate, and shallow trench isolation (STI) regions in the semiconductor substrate defining an active region therebetween in the semiconductor substrate, with the active region having rounded shoulders adjacent the STI regions with an interior angle of at least 125°. The semiconductor device may further include a superlattice on the active region including stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may also include a semiconductor circuit on the substrate including the superlattice.
Abstract: In one aspect, a bridge includes a first magnetoresistance element having a first reference angle, a second magnetoresistance element in series with the first magnetoresistance element and having a second reference angle, a third magnetoresistance element in parallel with the first magnetoresistance element and having the first reference angle and a fourth magnetoresistance element in series with the third magnetoresistance element and having the second reference angle. An output of the bridge has a linear response over a range of horizontal magnetic field intensity values not centered about a zero value and a reference angle indicates an angle the magnetoresistance element is most sensitive to changes in a magnetic field.
Abstract: A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor.
Abstract: A semiconductor apparatus includes: a metal plate; a semiconductor device mounted on the metal plate; an external terminal electrically connected to the semiconductor device or the metal plate; a metal wire wire-bonded to the semiconductor device, the metal plate or the external terminal; and a package covering and resin-sealing the semiconductor device, the metal plate and the metal wire, wherein the metal wire is bonded to a top-layer electrode of the semiconductor device at a first bond and a second bond, and the metal wire includes a low loop that is positioned between the first bond and the second bond, is adjacent to at least one of the first bond and the second bond and is not in contact with the top-layer electrode.
Abstract: A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.
Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.
Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.
Abstract: The invention discloses crossing structures of an integrated transformer or an integrated inductor. The crossing structures can be applied to various integrated transformers or integrated inductors. The crossing structures disclosed in the present invention includes multiple segments fabricated on a first metal layer of the semiconductor structure and multiple segments fabricated on a second metal layer of the semiconductor structure, the first metal layer being different from the second metal layer.
Abstract: A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.