Patents Examined by Douglas W. Owens
  • Patent number: 11929308
    Abstract: In a described example, an apparatus includes: a package substrate for mounting a semiconductor die to a die side surface, the package substrate including leads spaced from one another; and cavities extending into the leads from the die side surface, the cavities having sides and a bottom surface of the lead material, the cavities at locations corresponding to post connect locations on the semiconductor die.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 12, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steffany Ann Lacierda Moreno, John Carlo Cruz Molina, Rafael Jose Lizares Guevara
  • Patent number: 11929278
    Abstract: Exemplary substrate support assemblies may include an electrostatic chuck body that defines a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. A density of the plurality of protrusions within an outer region of the substrate support surface may be greater than in an inner region of the substrate support surface. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include an electrode embedded within the electrostatic chuck body.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 12, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Madhu Santosh Kumar Mutyala, Saketh Pemmasani, Akshay Dhanakshirur, Mayur Govind Kulkarni, Hang Yu, Deenesh Padhi
  • Patent number: 11923327
    Abstract: A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: March 5, 2024
    Assignee: Rockley Photonics Limited
    Inventors: Michael Lee, John Paul Drake, Ying Luo, Vivek Raghunathan, Brett Sawyer
  • Patent number: 11923326
    Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Yu Chang, Ming-Da Cheng, Ming-Hui Weng
  • Patent number: 11917875
    Abstract: A display device includes a substrate including an active area having pixels and a non-active area including a pad region. A pad electrode is disposed in the pad region and includes a first pad electrode and a second pad electrode disposed on the first pad electrode. A first insulating pattern is interposed between the first and second pad electrodes. In a plan view, the first insulating pattern is positioned inside the first pad electrode, and a portion of the second pad electrode overlapping the first insulating pattern protrudes further from the substrate in a thickness direction than a portion of the second pad electrode not overlapping the first insulating pattern. The second pad electrode directly contacts a portion of the upper surface of the first pad electrode. In a plan view, an area of the second pad electrode is greater than an area of the first pad electrode.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Kyung Youk, Chan Jae Park, Min Soo Kim, Yoon A Kim, Sang Duk Lee, Chel Gou Lim
  • Patent number: 11916039
    Abstract: Techniques are disclosed for facilitating interconnecting semiconductor devices. In one example, a method of interconnecting a first substrate to a second substrate is provided. The method includes forming a first plurality of contacts on the first substrate. The method further includes forming an insulative layer on the first substrate. The method further includes forming a second plurality of contacts on the second substrate. The method further includes joining the first plurality of contacts to the second plurality of contacts to form interconnects between the first substrate and the second substrate. When the first and second substrates are joined, at least a portion of each of the interconnects is surrounded by the insulative layer. Related systems and devices are also provided.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: February 27, 2024
    Assignee: Teledyne FLIR Commercial Systems, Inc.
    Inventors: Richard E. Bornfreund, Edward K. Huang
  • Patent number: 11917893
    Abstract: A mask plate, a method for manufacturing a mask plate, and a method for manufacturing an organic light-emitting device are disclosed. The mask plate includes a substrate and a first opening portion and a second opening portion formed on the substrate. The first opening portion includes a first edge and a second edge, an extending line of the first edge and an extending line of the second edge intersect at a first vertex to form a first corner, the second opening portion is at the first corner and protrudes outward, and an edge of the second opening portion intersects with the first edge and the second edge. The first opening portion and the second opening portion are used for evaporation on a display area of an organic light-emitting device, and the second opening portion is used to compensate for a corner of the display area during evaporation.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: February 27, 2024
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peng Xu, Jiangtao Deng, Fengli Ji
  • Patent number: 11916097
    Abstract: A display apparatus with a detection device comprising: a substrate having a first principal surface and a second principal surface opposite to the first principal surface; a plurality of inorganic light-emitting elements provided on the first principal surface in a display region of the substrate; a first electrode facing the first principal surface of the substrate with the inorganic light-emitting elements interposed between the first electrode and the first principal surface; a first planarizing layer provided between the substrate and the first electrode and covering at least a side surface of the inorganic light-emitting elements; and a second electrode facing the second principal surface of the substrate and configured to output a signal corresponding to a change in distance between the second electrode and the first electrode.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: February 27, 2024
    Assignee: Japan Display Inc.
    Inventors: Masanobu Ikeda, Yasuhiro Kanaya
  • Patent number: 11910712
    Abstract: The present application relates to a compound represented by Chemical Formula 1, an organic optoelectronic diode and a display device.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: February 20, 2024
    Assignee: LT MATERIALS CO., LTD.
    Inventors: Hye-Su Ji, Seong-Jong Park, Won-Jang Jeong
  • Patent number: 11908818
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
  • Patent number: 11894325
    Abstract: A semiconductor device includes a semiconductor layer that has a main surface, an electrode pad that is formed on the main surface, a rewiring that has a first wiring surface connected to the electrode pad and a second wiring surface positioned on a side opposite to the first wiring surface and being roughened, the rewiring being formed on the main surface such as to be drawn out to a region outside the electrode pad, and a resin that covers the second wiring surface on the main surface and that seals the rewiring.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: February 6, 2024
    Assignee: ROHM CO., LTD.
    Inventor: Manato Kurata
  • Patent number: 11894331
    Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes an interconnect layer over the substrate. The chip structure includes a conductive pad over the interconnect layer. The chip structure includes a conductive bump over the conductive pad. The conductive bump has a first portion, a second portion, and a neck portion between the first portion and the second portion. The first portion is between the neck portion and the conductive pad. The neck portion is narrower than the first portion and narrower than the second portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Cheng Chen, Pei-Haw Tsao
  • Patent number: 11890702
    Abstract: The present invention provides a highly reliable solder joint, the solder joint including a solder joint layer having a melted solder material containing Sn as a main component and further containing Ag and/or Sb and/or Cu; and a joined body including a Ni—P—Cu plating layer on a surface in contact with the solder joint layer, wherein the Ni—P—Cu plating layer contains Ni as a main component and contains 0.5% by mass or greater and 8% by mass or less of Cu and 3% by mass or greater and 10% by mass or less of P, the Ni—P—Cu plating layer has a microcrystalline layer at an interface with the solder joint layer, and the microcrystalline layer includes a phase containing microcrystals of a NiCuP ternary alloy, a phase containing microcrystals of (Ni,Cu)3P, and a phase containing microcrystals of Ni3P.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 6, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hirohiko Watanabe, Shunsuke Saito, Takeshi Yokoyama
  • Patent number: 11894358
    Abstract: In a semiconductor device, a substrate has a main surface. A first semiconductor chip has a first front surface and a first back surface, and is mounted on the main surface via a plurality of bump electrodes. A first spacer has a second front surface and a second back surface that is mounted on the main surface. A height of the second front surface from the main surface is within a range between a highest height and a lowest height of the first back surface from the main surface. A second spacer has a third front surface and a third back surface that is mounted on the main surface. A height of the third front surface from the main surface is within the range between the highest height and the lowest height of the first back surface from the main surface.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: February 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Masayuki Miura
  • Patent number: 11887958
    Abstract: A die including a first contact with a first shape (e.g., ring-shaped) and a second contact with a second shape (e.g., cylindrical shaped) different from the first shape. The first contact has an opening that extends through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact and the first solder portion has the first shape. A second solder portion is coupled to a surface of the second contact and the second solder portion has the second shape. The first solder portion and the second solder portion both have respective points furthest away from a substrate of the die. These respective points of the first solder portion and the second solder portion are co-planar with each other such that a standoff height of the die remains consistent when coupled to a PCB or an electronic component.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 30, 2024
    Assignee: STMICROELECTRONICS LTD
    Inventor: Cheng-Yang Su
  • Patent number: 11887956
    Abstract: A semiconductor device and formation thereof. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a plurality of pillars interconnecting the first semiconductor structure and the second semiconductor structure. The plurality of pillars include a first solder layer and a second solder layer, wherein the first solder layer has a higher melting point than the second solder layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: January 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Katsuyuki Sakuma, Mukta Ghate Farooq
  • Patent number: 11887950
    Abstract: A solid-state imaging device to be provided includes a first semiconductor device including a semiconductor layer in which a photoelectric conversion unit that photoelectrically converts incident light and a penetrating via are provided, a first connecting portion and a second connecting portion on the surface side of the semiconductor layer on the side that receives the light, and a connecting wiring line that connects the first connecting portion, the second connecting portion, and the penetrating via. The solid-state imaging device further includes a second semiconductor device that is mounted on the first semiconductor device with the first connecting portion. The solid-state imaging device is connected to an external terminal by the second connecting portion.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 30, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Takuya Nakamura
  • Patent number: 11881461
    Abstract: In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 23, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Enis Tuncer
  • Patent number: 11876065
    Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Katleen Fajardo Timbol, Salvatore Frank Pavone, Rafael Jose Lizares Guevara
  • Patent number: 11876061
    Abstract: Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: January 16, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yasuki Aihara