Patents Examined by Douglas W. Owens
  • Patent number: 11127854
    Abstract: A semiconductor device includes a semiconductor part, an first electrode, a control electrode and second electrodes. The control electrode and the second electrodes are provided between the semiconductor part and the first electrode, and provided inside trenches, respectively. The second electrodes include first to third ones. The first and second ones of the second electrodes are adjacent to each other with a portion of the semiconductor part interposed. The second electrodes each are electrically isolated from the semiconductor part by a insulating film including first and second insulating portions adjacent to each other. The first insulating portion has a first thickness. The second insulating portion has a second thickness thinner than the first thickness. The first insulating portion is provided between the first and second ones of the second electrodes. The second insulating portion is provided between the first and third ones of the second electrodes.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 21, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Katou, Atsuro Inada, Tatsuya Shiraishi, Tatsuya Nishiwaki, Kenya Kobayashi
  • Patent number: 11114371
    Abstract: A substrate-on-substrate structure and an electronic device including the same are provided. The substrate-on-substrate structure includes: a first printed circuit board having a first side and a second side; a second printed circuit board disposed on the second side of the first printed circuit board, and having a first side connected to the second side of the first printed circuit board and a second side opposite to the first side connected to the second side of the first printed circuit board; a reinforcing structure attached to the first side of the second printed circuit board, and spaced apart from the second side of the first printed circuit board; and an underfill resin disposed between the second side of the first printed circuit board and the first side of the second printed circuit board, and covering at least a portion of the reinforcing structure.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yong Hoon Kim, Seung Eun Lee, Young Kwan Lee, Hak Chun Kim
  • Patent number: 11107900
    Abstract: A dual-gate transistor and its production method are disclosed. An auxiliary gate is connected to the power supply of the integrated circuits, to form thick and high square-shaped potential barrier of minority carriers adjacent to the drain electrode, while the potential barrier is transparent for the majority carriers from the source electrodes. The potential barrier can effectively inhibit reverse minority carrier tunneling from the drain electrode at large drain-source voltage. The transistor can be easily turned on at small drain-source voltage, without significantly decreasing the on-state current. The dual-gate transistor can significantly suppress ambipolar behavior with increased current on/off ratio and reduced power consumption, and maintain the high performance. Based on transistors, strengthened CMOS circuits can have high noise margin, low voltage loss, reduced logic errors, high performance and low power consumption.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: August 31, 2021
    Assignee: Peking University
    Inventors: Chenyi Zhao, Donglai Zhong, Zhiyong Zhang, Lianmao Peng
  • Patent number: 11101228
    Abstract: Aspects of the present disclosure provide an integrated circuit package having an inductive element with a magnetic core. An example integrated circuit package generally includes a semiconductor die, a redistribution layer, and a magnetic core. The semiconductor die includes a metal layer having first conductive traces and conductive pillars coupled to and extending from the metal layer. The redistribution layer is disposed below the semiconductor die and includes second conductive traces. A portion of the first conductive traces, a portion of the conductive pillars, and a portion of the second conductive traces are arranged to form an inductive element disposed below a portion of the semiconductor die. The magnetic core is disposed in the inductive element.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Jonghae Kim, Milind Shah, Periannan Chidambaram
  • Patent number: 11088308
    Abstract: A bonding structure is a bonding structure which bonds a light emitting element and a substrate and includes a first electrode formed on the light emitting element, a second electrode formed on the substrate, and a bonding layer which bonds the first electrode and the second electrode, and the bonding layer contains a first bonding metal component and a second bonding metal component different from the first bonding metal component.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 10, 2021
    Assignee: TDK CORPORATION
    Inventors: Takasi Satou, Susumu Taniguchi, Hideyuki Kobayashi, Makoto Orikasa
  • Patent number: 11081556
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating layer provided on a surface of the silicon carbide substrate, a gate electrode provided on the gate insulating layer, a first insulting layer provided on the gate electrode, a first layer provided on the first insulating layer, a second insulating layer provided on the first insulating layer, and an interconnect layer provided on the second insulating layer. The second insulating layer includes SiN or SiON. The first layer includes one of Ti, TiN, Ta, and TaN. The interconnect layer includes Al or Cu.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: August 3, 2021
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hiroyuki Kamada
  • Patent number: 11081452
    Abstract: A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 3, 2021
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Chihoko Akiyama
  • Patent number: 11069650
    Abstract: The apparatus which assists in deriving bonding conditions includes a bonding unit which bonds a semiconductor chip and a substrate by applying heat and pressure with NCF interposed therebetween, a library in which a variety of physical property information including viscosity characteristic information is collected with respect to each of a plurality of types of NCFs, an initial evaluation condition determination unit which acquires the physical property information corresponding to the NCF used for bonding with reference to the library and determines an initial value of an evaluation condition of bonding evaluation performed by bonding the semiconductor chip and the substrate, and a bonding evaluation unit which drives the bonding unit in accordance with set evaluation condition, bonds the semiconductor chip and the substrate and performs the bonding evaluation at least once to measure the viscosity of the NCF at the time of the bonding.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 20, 2021
    Assignee: SHINKAWA LTD.
    Inventor: Tomonori Nakamura
  • Patent number: 11063011
    Abstract: A chip includes pads having first connecting surfaces, and conductive structures located on the first connecting surfaces. The conductive structures are disposed on the first connecting surfaces. Each of the conductive structures includes first metal layer, second metal layer, and third metal layer. The first metal layer connects one of the pads, and the second metal layer is disposed between the first metal layer and the third metal layer. On every pad, the first metal layer, the second metal layer, and the third metal layer are stacked along first direction on the first connecting surface of the pad, and the first direction is parallel to normal direction of the first connecting surface, and the first metal layer is made of material comprising gold, and the second metal layer is made of material comprising nickel. A wafer is also provided.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: July 13, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chia-Lin Tsai, Mao-Ying Wang
  • Patent number: 11056592
    Abstract: An integrated circuit (IC) includes a substrate that includes silicon. A first layer is on the substrate and includes a first monocrystalline semiconductor material, the first layer having a plurality of defects. A second layer is on the first layer and includes a second monocrystalline semiconductor material that includes germanium. A strained channel structure is above the first layer. A gate structure is at least above the channel structure. A source region is adjacent the channel structure. A drain region is adjacent the channel structure, such that the channel structure is laterally between the source region and the drain region.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Cory C. Bomberger, Glenn A. Glass, Anand S. Murthy, Ju H. Nam, Tahir Ghani
  • Patent number: 11049792
    Abstract: A semiconductor device package includes a heatsink platform, with a ceramic isolation layer bonded to the heatsink platform. A semiconductor die may be disposed on the ceramic isolation layer, with mold material disposed on the ceramic isolation layer and surrounding at least a portion of the semiconductor die. A redistribution layer may be disposed on the semiconductor die and the mold material. Such packages, and similar, enable the use of a thin, inexpensive device substrate, while providing an efficient thermal path to the heatsink platform, while the redistribution layer enables electrical connections that are short, low-resistance, low-inductance, and low-loss connections.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: June 29, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gareth Pryce Weale, Joseph Steffler, Yik Yee Tan
  • Patent number: 11049964
    Abstract: A first portion of the poly-silicon layer is provided on a first face of a front surface of a semiconductor substrate via a gate insulating film in an edge termination region and configures a gate runner. The first portion opposes an edge p++-type contact region in a depth direction Z. A chip-end-side edge of the first portion is positioned within a plane of the edge p++-type contact region. A field oxide film disposed separated from the poly-silicon layer, extends from a chip end toward a chip center and, on the first face, terminates closer to the chip end than does the first portion. The entire surface of the poly-silicon layer is flat, free of a step due to the field oxide film. A chip-center-side edge of the field oxide film is closer to the chip end than is the edge p++-type contact region and positioned on a p-type base region.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 29, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tsuyoshi Araoka
  • Patent number: 11004952
    Abstract: A high-electron mobility transistor includes a substrate; a buffer layer on the substrate; a AlGaN layer on the buffer layer; a passivation layer on the AlGaN layer; a source region and a drain region on the AlGaN layer; a source layer and a drain layer on the AlGaN layer within the source region and the drain region, respectively; a gate on the AlGaN layer between the source region and a drain region; and a field plate on the gate and the passivation layer. The field plate includes an extension portion that laterally extends to an area between the gate and the drain region. The extension portion has a wave-shaped bottom surface.
    Type: Grant
    Filed: December 1, 2019
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Tung Yeh, Shin-Chuan Huang, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 11005445
    Abstract: An electronic component including a pad electrode provided on a wiring electrode and a Au bump provided on the pad electrode, wherein the uppermost layer of the wiring electrode is a first Ti layer, the uppermost layer of the pad electrode is a Au layer, and the thickness of the first Ti layer in at least a portion on which the Au bump is superposed in plan view is greater than the thickness of at least a portion of the first Ti layer in a portion on which the Au bump is not superposed in plan view.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 11, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryuta Yamada, Yasuyuki Toyota, Masaharu Fujiya, Toru Takeshita, Masaaki Shimada
  • Patent number: 10582582
    Abstract: A control system for a stadium lighting system comprising a plurality of luminaires installed within the stadium to illuminate a pitch within the stadium in accordance with a light plan containing aiming information for each luminaire is disclosed. The control system comprises a data storage device storing the light plan and a controller communicatively coupled to the data storage device, the controller being responsive to object tracking information for an object travelling across the pitch. The controller is adapted to determine a direction of travel of the object from the object tracking information; evaluate the aiming information for each luminaire to identify if at least one luminaire is arranged to generate a luminous output in an aiming direction coinciding with said direction of travel; and generate a dimming level adjustment signal for the at least one identified luminaire to reduce the intensity of said luminous output.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: March 3, 2020
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Harry Broers, Willem Peter Van Der Brug, Ruben Rajagopalan
  • Patent number: 10575383
    Abstract: An imaging sensor determines an influence of artificial light from one or more artificial light sources and an influence of natural light in an area associated with a lighting system. On the basis of the influence of the natural light and the influence of the artificial light, the imaging sensor determines the location of the one or more artificial light sources with respect to the location of the imaging sensor. Further, the imaging sensor allocates a portion of the area as an area of influence of the imaging sensor based on a threshold change in luminescence of the area associated with switching on or switching off of the one or more artificial light sources. Responsively, the imaging sensor associates at least one artificial light source of the one or more light sources and occupancy sensors corresponding to the at least one artificial light source with the allocated area of influence.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 25, 2020
    Assignee: Eaton Intelligent Power Limited
    Inventor: Kenneth Dale Walma, Jr.
  • Patent number: 10566168
    Abstract: One or more pellicles protect a cathode, the pellicles comprised of a thin layer of material that allows electrons to pass while preventing contamination of the cathode from elements originating beyond the pellicle or contamination of an outside apparatus from elements originating on or near the cathode. The pellicle can be supported by an insulator, the insulator in turn supported by a deflecting layer. The pellicle can be maintained at a positive voltage relative to the cathode, such that a voltage gradient is created between the cathode and the pellicle that accelerates electrons emitted by the cathode away from the cathode. The pellicle is located at an appropriate distance from the cathode to allow electron transmission matching the energy of the electrons at that distance.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: February 18, 2020
    Inventor: John Bennett
  • Patent number: 10560995
    Abstract: The invention relates to a method for configuring a lighting system including a set of at least 3 light sources (Li) having different spectra (Si(?)), including a step of automatically defining the intensities (?i) of each of the light sources of said set by minimising a distance between a reference spectrum (SR(?)) and a synthetic spectrum (Ss(?)) defined by the sum of the spectra (Si(?)) of each source (Li) of said set weighted by said intensities (?i).
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: February 11, 2020
    Assignee: WATTLUX
    Inventors: Patrick Belin, Yannick Bailly
  • Patent number: 10548191
    Abstract: Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system can include a driver and at least one SST module electrically coupled to the driver. Each SST module can include an SST and a sense resistor. The sense resistors of each SST module can have at least substantially similar resistance values. The SSTs of the SST modules can be coupled in parallel across an SST channel to the driver, and the sense resistors of the SST modules can be coupled in parallel across a sense channel to the driver. The driver can be configured to measure a sense resistance across the sense resistors and deliver a current across the SSTs based on the sense resistance.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Steven A. McMahon
  • Patent number: 10540885
    Abstract: The present disclosure generally relates to the field of fire alarms. The teachings thereof may be embodied in a strobe notification appliance having: a boost circuit connected to an input voltage; an energy storage circuit charged by the boost circuit; a drive circuit generating a drive current; an LED circuit with at least one LED element; a first sampling circuit collecting an overall voltage drop of all the LED elements; and a control circuit configured to adjust the drive circuit to supply a working current during an alarming stage and supply a detection current during a detection stage. The detection current is lower than the working current and thereby light energy produced by the LED elements during the detection stage is lower than alarming light energy produced during the alarming stage. During the detection stage, the control circuit determines whether the LED circuit works normally based on the collected overall voltage drop.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 21, 2020
    Assignee: SIEMENS SCHWEIZ AG
    Inventors: Hong Xiang Liang, Xue Song Shen, Jian Tan