Abstract: An electronic substrate and an electronic device are provided. The electronic substrate includes a base, a protruding portion, and a bonding pad. The protruding portion and the bonding pad are disposed on the base. The bonding pad is not overlapped with a boundary of the protruding portion.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.

Abstract: The present disclosure describes an organic-inorganic metal-halide-based semiconducting material that melts at lower temperatures compared to conventional inorganic semiconductors. The hybrid material is structurally engineered to easily access both crystalline and amorphous glassy states, with each state offering distinct physical properties.

Abstract: An etchant capable of selectively etching copper and a copper alloy while suppressing dissolution of nickel, tin, gold, and an alloy thereof. The etchant contains: (A) 5-10.5% by mass of hydrogen peroxide with respect to the total mass of the etchant; (B) 0.3-6% by mass of nitric acid with respect to the total mass of the etchant; (C) at least one nitrogen-containing 5-membered ring compound selected from triazoles and tetrazoles, which may have at least one substituent selected from a C1-6 alkyl group, an amino group, and a substituted amino group having a substituent selected from a C1-6 alkyl group and a phenyl group; and (D) (d1) one or more pH adjusters selected from an alkali metal hydroxide, ammonia, an amine, and an ammonium salt, (d2) a phosphoric acid compound, or (d3) a combination of (d1) and (d2).

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.

Abstract: A semiconductor package includes: a substrate; a first dielectric layer over the substrate; a first bond pad and a second bond pad over the first dielectric layer, the first bond pad having a first sidewall facing the second bond pad; a second dielectric layer over the first and the second bond pads; and an opening through the second dielectric layer and extending from the first bond pad to the second bond pad, the opening including a first area over and exposing the first bond pad, where in a top view, the opening exposes a first segment of the first sidewall disposed between a first edge and a second edge of the first area that intersect the first sidewall, where the first segment of the first sidewall is between a second segment and a third segment of the first sidewall, the second segment being covered by the second dielectric layer.

Abstract: A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

Abstract: A light-emitting diode display panel, a manufacturing method thereof, and an organic light-emitting diode display device are provided. The light-emitting diode display panel includes: a base substrate including a display region and a peripheral region surrounding the display region; a plurality of sub-pixels located in the display region and located at a side of the base substrate; a color-resistance layer located at a side of a second electrode in the sub-pixel away from the base substrate; and a light-blocking structure located in the peripheral region and being an annular structure surrounding the plurality of sub-pixels. The light-blocking structure includes a first light-blocking structure and a second light-blocking structure. The first light-blocking structure includes at least one interval extending in a direction from the display region pointing to the peripheral region. The second light-blocking structure at least fully fills the interval.

Abstract: The present disclosure relates to a redistribution layer (RDL) structure, a manufacturing method thereof, and a semiconductor structure having the same. The RDL structure includes an RDL, disposed on a substrate, and including a bond pad portion and a wire portion connected to the bond pad portion, where a thickness of the bond pad portion is greater than a thickness of the wire portion.

Abstract: The semiconductor device according to the present invention comprises; a semiconductor element having one surface with a plurality of electrode pads; an electrode structure including a plurality of metal terminals and a sealing resin. The plurality of metal terminals being disposed in a region along a circumference of the one surface. The sealing resin holding the plurality of metal terminals and being disposed on the one surface of the semiconductor element. The electrode structure includes a first surface opposed to the one surface of the semiconductor element, a second surface positioned in an opposite side of the first surface, and a third surface positioned between the first surface and the second surface. Each of the plurality of metal terminals is exposed from the sealing resin in at least a part of the second surface and at least a part of the third surface.

Abstract: A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor in which a device layer has high crystalline quality. According to some embodiments, a hard mask layer is deposited covering a substrate. A first etch is performed into the hard mask layer and the substrate to form a cavity. A second etch is performed to remove crystalline damage from the first etch and to laterally recess the substrate in the cavity so the hard mask layer overhangs the cavity. A sacrificial layer is formed lining cavity, a blanket ion implantation is performed into the substrate through the sacrificial layer, and the sacrificial layer is removed. An interlayer is epitaxially grown lining the cavity and having a top surface underlying the hard mask layer, and a device layer is epitaxially grown filling the cavity over the interlayer. A photodetector is formed in the device layer.

Abstract: A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.

Abstract: The present disclosure provides a chip structure, a packaging structure and a manufacturing method for the chip structure. The chip structure includes at least one chip body, each of which includes at least one radio frequency front-end device; the chip structure further includes a redistribution layer stacked on the chip body and at least one pin on the redistribution layer; each radio frequency front-end device corresponds to one pin, which is electrically connected to the radio frequency front-end device through an electrical connector extending through the redistribution layer; an extending direction of the radio frequency front-end device is consistent with an extending direction of the pin corresponding to the radio frequency front-end device; a surface of the pin distal to the redistribution layer is a first plane. In the present disclosure, with the first plane, the chip may be directly and electrically connected to a flexible circuit board.

Abstract: A semiconductor device includes: a first insulating film provided in a trench reaching a second semiconductor layer from above the second semiconductor region; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film; the second insulating film being provided between the side surface of the second electrode and a fifth insulating film provided between a side surface of the second electrode and the second semiconductor layer, the second insulating film containing a second insulating material having a higher dielectric constant than the first insulating material; a third electrode provided above the second electrode, the first insulating film and the second insulating film, the third electrode facing the first semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided above the interlayer insulating film.

Abstract: A semiconductor package includes: a semiconductor chip including a chip pad on a first surface; a first insulating layer arranged on the semiconductor chip and including an insulating hole exposing the chip pad; a redistribution pattern including a redistribution via pattern arranged on an internal surface of the first insulating layer configured to define the first insulating hole and on a surface of the chip pad, and a redistribution line pattern arranged on a surface of the first insulating layer; an under bump metal (UBM) conformally arranged along a surface of the redistribution pattern; and a connection terminal arranged on the UBM, wherein the redistribution line pattern and the UBM provide a dummy space of a shape protruding in a direction toward the first surface of the semiconductor chip, and a portion of the connection terminal fills the dummy space.

Abstract: A semiconductor device includes an SiC semiconductor substrate including a diffusion layer, a first electrode provided on the SiC semiconductor substrate, a second electrode provided on the first electrode, and a resin section that is substantially the same size in a plan view as the SiC semiconductor substrate, and that is configured to seal in the second electrode.

Abstract: A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.