Patents Examined by Douglas W. Sergent
  • Patent number: 6370495
    Abstract: The present invention simulates the behavior of a storage component by first determining whether a timing violation has occurred for the storage component. If one or more timing violations is detected, then an x (indicating uncertainty) is reflected at the output of the storage component. This x is maintained at the output of the storage component for a predetermined number of timing units. After the predetermined number of timing units has expired, the output of the storage component is changed from x to a certain value, such as a logical 1 or a logical 0. By changing the output to a certain value, the present invention prevents the x at the output of the storage component from indefinitely propagating to other components in the circuit. This in turn prevents large numbers of x's from appearing in the simulation results provided to the designer. Instead, values that are certain will appear in the results.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: April 9, 2002
    Assignee: Oak Technology
    Inventors: Eugene Weddle, Roy Wen, Bernard E. Stewart, Singh Shashij
  • Patent number: 6336088
    Abstract: Method and apparatus for synchronizing the execution of the two or more test lists at desired synchronization points, while allowing the test lists to execute in a non-deterministic manner between the synchronization points is disclosed. A test driver is provided for executing each test list, and a run controller is provided for monitoring the execution of each test list. To synchronize the execution of the two or more test lists, the run controller halts the execution of each test list as each test driver assumes a predetermined state. Once all of the test lists are halted, the test lists are synchronized. Once synchronized, selected test drivers are restarted to continue execution of the corresponding test lists in a relatively non-deterministic manner.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: January 1, 2002
    Assignee: Unisys Corporation
    Inventors: Mitchell A. Bauman, Douglas H. Bloom, Joseba M. Desubijan, Larry L. Byers
  • Patent number: 6324495
    Abstract: A synchronous parallel system for emulation and discrete event simulation having parallel nodes responds to received messages at each node by generating event objects having individual time stamps, stores only the changes to the state variables of the simulation object attributable to the event object and produces corresponding messages. The system refrains from transmitting the messages and changing the state variables while it determines whether the changes are superseded, and then stores the unchanged state variables in the event object for later restoral to the simulation object if called for. This determination preferably includes sensing the time stamp of each new event object and determining which the new event object has the earliest time stamp as the local event horizon, determining the earliest local event horizon of the nodes as the global event horizon, and ignoring events whose time stamps are less than the global event horizon.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: November 27, 2001
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventor: Jeffrey S. Steinman
  • Patent number: 6324493
    Abstract: A so-called multipole decomposition is employed for modeling the charge and current distributions and the interactions of those distributions in metalization sub units arising from electrical signals in those metalization sub units. Specifically, a variable interaction range meshing, i.e., multipole, decomposition process is advantageously employed to model the charge and current distributions of metalization sub units. These distributions are then employed to obtain electrical characteristics of an overall physical metalization structure to be fabricated. In an embodiment of this invention, representative sections of metalization sub units are selected such as straight sections of infinitesimal length, right angle bends and intersections, and solved for the local short range charge and current interactions that determine their local distributions in those sub units.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: November 27, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventor: Nathan R. Belk
  • Patent number: 6321185
    Abstract: Power consumption of an LSI chip is estimated at the beginning stage of the designing without using the HDL description. An I/O part power of a new designing LSI chip is calculated by an equation with using the outside specifications required by the application of the LSI chip. An I/O part power of an original LSI chip is calculated by the outside specifications, the core circuitry part power of the original LSI chip is calculated by subtracting this calculated I/O part power of the original LSI chip from the known total power of the original LSI chip, and converting the voltage and process and frequency, the core circuitry part power of the new designing LSI chip is calculated.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventor: Naoya Takahashi
  • Patent number: 6321184
    Abstract: A method of generating a digital circuit model that has fewer latches than the circuit being modeled. Initially, a determination of whether the digital circuit is reducible is made. The digital circuit suitably includes one or more primary inputs, one or more primary outputs, and a plurality of latches comprised of a level one (L1) latch set and a level two (L2) latch set wherein the latch sets may or may not lack one-to-one correspondence. After determining that the digital circuit is reducible, at least one of the latches is replaced with combinational logic thereby reducing the latch count of the digital circuit model.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: November 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jason Raymond Baumgartner, Tamir Heyman
  • Patent number: 6321186
    Abstract: A method for verifying an integrated circuit design using constraint information to develop a weighted data structure. In one embodiment, a binary decision diagram (BDD) includes a plurality of nodes (401, 402, 403, 404, 405, 406, 407, 420, and 430) representing signals and states in the circuit, and each node has a branching probability based on user-defined weights. The BDD represents the intersection of the input space and state space which satisfies the constraints. Current state information resulting from simulation is used to dynamically adjust the branching probabilities of the BDD on the fly. In one embodiment, the constraint information is applicable for formal verification of a portion of the circuit. In another embodiment, a simulation controller (12) receives design and constraint information and generates the program to control simulator (14).
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: November 20, 2001
    Assignee: Motorola, Inc.
    Inventors: Jun Yuan, Carl P. Pixley, Stephen Kurt Shultz, Hillel Miller
  • Patent number: 6311142
    Abstract: An interactive development environment for design and placement of tiered geometrical objects, such as objects used in pop-up card designs. Relations between objects are represented mathematically, allowing computerized modeling and enforcement of design constraints. For example, in the context of pop-up cards, a card that cannot close will not be allowed. A dependency hierarchy is used to track different objects of a card. Card objects are instantiated as related to other card objects so that changes to one card object can be appropriately propagated to related objects. If all card objects are defined with respect to a base card, an entire card design can be animated by only adjusting, e.g., “opening” and “closing,” the base card. A graphical interface provides drag-and-drop and manual forms of placing card parts. For drag-and-drop, design constraints can be used to automatically determine proper positioning of card pieces.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: October 30, 2001
    Assignee: Microsoft Corporation
    Inventor: Andrew S. Glassner
  • Patent number: 6298317
    Abstract: A function simulates and verifies a computer program by inserting a syntactic mutation into one of the source code modules comprising the program. The mutated computer program is compiled and subjected to a subtlety check which detects non-subtle (i.e., easily detectable) syntactic mutations. If the subtlety check identifies the inserted syntactic mutation as non-subtle, functional testing on this mutated computer program is terminated, and a new mutated computer program is generated. However, if the subtlety check determines that the syntactic mutation is subtle, the mutated computer program is subjected to additional regression testing. If the regression testing is able to detect the subtle syntactic mutation within a predetermined simulation period, functional testing is terminated and a new mutated computer program is generated.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: October 2, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Alan Wiemann
  • Patent number: 6295516
    Abstract: A data transmission apparatus and a data transmission system, and more particularly, a data transmission apparatus which includes a detection unit for detecting a bandwidth of data transmission actually used in a transmission line, a calculation unit for calculating a bandwidth required for transmission of data to be transmitted, and a requesting means for requesting, when the bandwidth of data transmission actually used in the transmission line varies, a management apparatus for the transmission line to set a bandwidth in the transmission line in response to the bandwidth calculated by the calculation means.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: September 25, 2001
    Assignee: Sony Corporation
    Inventor: Masashi Takeyasu
  • Patent number: 6292763
    Abstract: A method for designing a variable cycle gas turbine engine having a fan assembly with a maximum air flow there through and a maximum pressure ratio there across during operation at a fan speed and a plurality of variable pitch vanes, which method includes the steps of selecting a first operating point of the variable cycle gas turbine engine at a fan speed having about maximum air flow through the fan assembly at a pressure ratio substantially less than maximum pressure ratio and selecting a second operating point of the variable cycle gas turbine engine at about the fan speed, wherein the second operating point has about the maximum pressure ratio across the fan assembly at an air flow through the fan assembly substantially less than the maximum air flow. A reference point having a reference air flow through the fan assembly and a reference pressure ratio across the fan assembly is selected.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: September 18, 2001
    Assignee: Diversitech, Inc.
    Inventors: Donald K. Dunbar, Marlen L. Miller, George L. Converse
  • Patent number: 6292765
    Abstract: A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: September 18, 2001
    Assignee: O-In Design Automation
    Inventors: Chian-Min Richard Ho, Robert Kristianto Mardjuki, David Lansing Dill, Jing Chyuarn Lin, Ping Fai Yeung, Paul II Estrada, Jean-Charles Giomi, Tai An Ly, Kalyana C. Mulam, Lawrence Curtis Widdoes, Jr., Paul Andrew Wilcox
  • Patent number: 6292766
    Abstract: The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file generator permits a user to conveniently enter high level circuit description information in user friendly formats such as an easy to use GUI. Based upon the information provided by a user, the present invention assembles data including circuit description files stored in a memory and produces a detailed simulation tool input files.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: September 18, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Derwin Mattos, Henry Jen, Saeid Moshkelani
  • Patent number: 6289300
    Abstract: A data processor is provided with an embedded debugger. The debugging function is provided by the execution of a debugging program which is stored in reserved, non-volatile memory which is internal to the data processor. During the debug mode, the data processor allows the internal registers used during execution of a user program to be examined. Debug operation can be initiated via debug instruction which replaces an existing instruction in the user code, the replaced instruction being held in a special purpose register such that it can be executed on return from the debug mode. Single step operation of the data processor can be performed in debug mode and data and instructions can be exchanged with the data processor in debug mode, optionally via a single pin so as not to sacrifice any user resources.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: September 11, 2001
    Assignee: Analog Devices, Inc.
    Inventors: Dara Joseph Brannick, Patrick Michael Mitchell, Timothy J. Cummins, Brian John O'Mara
  • Patent number: 6289297
    Abstract: An adaptive region-based, multi-scale, motion compensated video compression algorithm design for transmission over hostile communication channels. The algorithm is embodied in a video encoder that extracts spatial information from video frames to create video regions that are then decomposed into sub-bands of different perceptual importance before being compressed and transmitted independently. The system further uses unequal error protection, prioritized transmission and reconstruction to guarantee a minimum spatial and temporal resolution at the receiver. In particular, the region segmented frames bound both spatial and temporal error propagation within frames. A connection-level inter-region statistical multiplexing scheme is also employed to ensure optimal utilization of reserved transmission bandwidth.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: September 11, 2001
    Assignee: Microsoft Corporation
    Inventor: Paramvir Bahl
  • Patent number: 6278966
    Abstract: A method and device to generate behavior for emulated visitors traversing an internet web site. The visitors may display behavior that is indistinguishable from those of actual users, a subset of the actual users, or the behavior may be purely hypothetical, such as when a visitor acts without evidence of having made an intentional choice. The invention tracks the actions of the visitors and develops reference distributions that may be compared to a site's usage distributions as obtained from actual visitors to the site. The reference distributions are then used to implement statistical estimation methods that measure relative information content. The invention comprises a general implementation and a deterministic implementation. The general version may be applied to live production web sites, and the deterministic version is best suited to offline processing.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: August 21, 2001
    Assignee: International Business Machines Corporation
    Inventors: Steven Kenneth Howard, David Charles Martin, Mark Earl Paul Plutowski
  • Patent number: 6272449
    Abstract: The present invention provides a description of the behavior of a model that indicates the sensitivity of the model in subspaces of the input space and which indicates which dimensions of the input data are salient in subspaces of the input space. By implementing this description using a decision tree, the subspaces and their salient dimensions are both described and determined hierarchically. A sensitivity analysis is performed on the model to provide a sensitivity profile of the input space of the model according to sensitivity of outputs of the model to variations in data input to the model. The input space is divided into at least two subspaces according to the sensitivity profile. A sensitivity analysis is performed on the model to provide a sensitivity profile of each of the subspaces according to sensitivity of outputs of the model to variations in data input to the model.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: August 7, 2001
    Assignee: Torrent Systems, Inc.
    Inventor: Anthony Passera
  • Patent number: 6266630
    Abstract: A method and apparatus for providing a graphical user interface for simulating designs with mixed signals is described. The present invention provides graphical information to a circuit designer as to the solution of the equation(s) that describe or model the design. The graphical information allows the designer to see convergence and convergence rates of the analog circuit simulation. By providing the designer with information related to the convergence of solutions for the modeling equations, the designer is better able to debug the design because he or she can view the timing and situations related to convergence and divergence.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: July 24, 2001
    Assignee: Mentor Graphics Corporation
    Inventors: Serge F. Garcia-Sabiro, Christophe P. Hui-Bon-Hoa, Polen Kission, Jean-Pierre Cirigliano, Philippe P. Raynaud
  • Patent number: 6266629
    Abstract: A method is provided for large signal modeling of a field effect transistor. The method includes establishing a small signal model for the transistor, such model having a gate-source capacitance Cgs and a drain-gate capacitance Cdg, both being functions of a gate-source voltage Vgs and a drain-source voltage Vds. The s-parameters of the transistor are measured and curve fitting is applied to the measured s-parameters to establish small signal model parameters. The small signal model parameters include gate-source capacitance Cgs as a function of Vgs and Vds and gate-drain capacitance Cdg as a function of Vgs and Vds. Curve fitting is applied to Cgs and Cdg to establish large signal gate charge fitting parameters. The established large signal gate charge fitting parameters are used to express a gate-source charge Qgs and a gate-drain charge Qgd as functions of Vgs and a gate-drain voltage Vgd in a large signal model for the transistor.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: July 24, 2001
    Assignee: Raytheon Company
    Inventors: Raghuveer Mallavarpu, Douglas A. Teeter
  • Patent number: 6263301
    Abstract: A method and apparatus for managing simulation results involves identifying distinct transactions in a group of simulation results so that the simulation results can be stored and viewed on a transaction basis instead of as a single continuous block of simulation results. A transaction is defined as a specific sequence of transitions on a selection or grouping of signals over a period of time where the signal activity has some higher level operational meaning. Simulation results are recorded on a transaction basis by storing standard simulation results information along with transaction-specific data elements, including the name of the transaction, the start time of the transaction, the end time of the transaction, and the interface on which the transaction takes place. Additional transaction-specific data elements may include parent and child relationships and predecessor and successor relationships between transactions.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: July 17, 2001
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven G. Cox, James M. Gallo, Mark Glasser