Patents Examined by Dustin B. Fulford
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Patent number: 11809710Abstract: A system includes a first controller configured to adjust a count of a number of first transactions and adjust a count of a number of second transactions. The count of the number of first transactions and the count of the number of second transactions are adjusted when a first transaction or second transaction is either received or executed by a second controller. The second controller is coupled to the first controller and is configured to limit the number of first transactions to a particular quantity of outstanding first transactions, limit the number of second transactions to a particular quantity of outstanding second transactions, and limit a number of total transactions to a particular quantity of outstanding total transactions.Type: GrantFiled: September 24, 2021Date of Patent: November 7, 2023Assignee: Micron Technology, Inc.Inventors: Dhawal Bavishi, Robert M. Walker, Laurent Isenegger
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Patent number: 11775436Abstract: One embodiment of a cache invalidation method includes storing an invalidation status usable by a computing node to identify, from a broadcast cache invalidation queue, a last processed invalidation that was processed with respect to an object cache used by the node. The method further comprises the node determining a set of unprocessed invalidations from the broadcast cache invalidation queue that are subsequent to the last processed invalidation determined from the invalidation status. The node processes the set of unprocessed invalidations to clear cached objects from the object cache. Based on processing the set of unprocessed invalidations to clear cached objects from the object cache, the invalidation status is updated with an identifier corresponding to a last invalidation from the set of previously unprocessed invalidations.Type: GrantFiled: October 25, 2021Date of Patent: October 3, 2023Assignee: Open Text SA ULCInventors: Michael Gerard Jaskiewicz, Sarah Barnes Atlas, Mukesh Chowdhary, Lloyd Douglas Forrest
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Patent number: 11775177Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.Type: GrantFiled: October 17, 2019Date of Patent: October 3, 2023Assignee: Arm LimitedInventors: Yuval Elad, Roberto Avanzi, Jason Parker
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Patent number: 11768763Abstract: A system with storage memory and a processing device has a logical deletion to physical erasure time bound. The system dereferences data, responsive to a direction to delete the data. The system monitors physical blocks in storage memory for live data and the dereferenced data. The system cooperates garbage collection with monitoring the physical blocks, so that at least a physical block having the dereferenced data is garbage collected and erased within a logical deletion to physical erasure time bound.Type: GrantFiled: July 8, 2020Date of Patent: September 26, 2023Assignee: PURE STORAGE, INC.Inventors: Igor Ostrovsky, Constantine P. Sapuntzakis, Peter E. Kirkpatrick, John Colgrove
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Patent number: 11748197Abstract: A data storage method includes partitioning a data into an array having a plurality of data blocks and storing the data blocks across a plurality of storage nodes. Parity blocks are encoded based on the data array by performing a shift operation on the data array to produce a shifted array and performing an exclusive OR (XOR) operation on the elements in each row of the shifted array to produce a parity block. The method further includes storing the parity blocks across a plurality of the storage nodes. Systems are configured to recover data from a data array in the event that the data array is at least partly inaccessible.Type: GrantFiled: January 30, 2020Date of Patent: September 5, 2023Assignees: QATAR FOUNDATION FOR EDUCATION, SCIENCE AND COMMUNITY DEVELOPMENT, QATAR UNIVERSITYInventors: Qutaibah Malluhi, Naram Mhaisen
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Patent number: 11733925Abstract: A request to program a set of host data items to management units (MUs) of a fault tolerant stripe associated with a memory sub-system is received. A set of memory access operations to be executed at the MUs of the fault tolerant stripe in accordance with the received request is determined. The set of memory access operations include one or more read operations to read data from the MUs of the fault tolerant stripe. The set of memory access operations also include one or more write operations to write the set of host data items and redundancy metadata associated with the set of host data items to MUs of the fault tolerant stripe. A first series of commands corresponding to the one or more read operations of the set of memory access operations is executed. The redundancy metadata associated with the set of host data items is generated based on the data read from the MUs of the fault tolerant stripe during execution of the first series of commands and the set of host data items.Type: GrantFiled: August 30, 2021Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Chih-Kuo Kao, Jiangli Zhu, Ying Yu Tai
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Patent number: 11733910Abstract: A method includes utilizing, while delivery of power from a main power supply to a memory sub-system is interrupted, a processing device of the memory subsystem to monitor a characteristic of the memory sub-system associated with data retention at a non-volatile memory component of the memory sub-system. The method further includes utilizing, while delivery of power from a main power supply to a memory sub-system is interrupted, a processing device of the memory subsystem to predict, based on the monitored characteristic, an impending data loss event for the non-volatile memory component.Type: GrantFiled: August 31, 2021Date of Patent: August 22, 2023Assignee: Micron Technology, Inc.Inventor: Nicholas T. Heath
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Patent number: 11726688Abstract: A storage system communicates with a host system and includes a storage device including storage medium divided into a plurality of blocks including high reliability blocks and reserve blocks, and a controller. The controller provides the host system with block information identifying the high reliability blocks among the plurality of blocks, receives a block allocation request from the host system, wherein the block allocation request is defined with reference to the block information and identifies at least one high reliability block to be used to store metadata, and allocates at least one high reliability block to a meta region in response to the block allocation request. The controller includes a bad block manager that manages an allocation operation performed in response to the block allocation request, and a repair module that repairs an error in metadata stored in one of the high reliability blocks.Type: GrantFiled: March 30, 2020Date of Patent: August 15, 2023Inventors: Jaeyoon Choi, Seokhwan Kim, Suman Prakash Balakrishnan, Dongjin Kim, Chansol Kim, Eunhee Rho, Hyejeong Jang, Walter Jun
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Patent number: 11720253Abstract: Methods, systems, and devices for access of a memory system based on fragmentation are described. The memory system may receive a first message indicating a set of data that the memory system is to store using a fragmentation-based write procedure. The memory system may, based on the first message, determine blocks of a memory device that satisfy a fragmentation threshold. After determining the blocks, the memory system may transmit to the host system a second message that indicates the memory system is ready to receive the set of data indicated in the first message. The memory system may then store the set of data in the determined blocks based on transmitting the second message.Type: GrantFiled: December 29, 2021Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Jun Huang, Bhagyashree Bokade, Violet Gomm, Deping He, Lavanya Sriram
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Patent number: 11709631Abstract: A system includes a processing device, operatively coupled with a memory device, to perform operations including receiving a media access operation command designating a first memory location, and determining whether a first media access operation command designating the first memory location and a second media access operation designating a second memory location are synchronized, after determining that the first and second media access operation commands are not synchronized, determining that the media access operation command is an error flow recovery (ERF) read command, in response to determining that the media access operation command is an ERF read command, determining whether a head command of the first queue is blocked from execution, and in response to determining that the head command is unblocked from execution, servicing the ERF read command from a media buffer maintaining previously written ERF data.Type: GrantFiled: August 30, 2021Date of Patent: July 25, 2023Assignee: Micron Technology, Inc.Inventors: Fangfang Zhu, Jiangli Zhu, Juane Li
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Patent number: 11693571Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory and a controller. The non-volatile memory includes a plurality of physical blocks. The controller is connected to any of the plurality of physical blocks via a plurality of channels. The controller is configured to construct a plurality of logical blocks and, read or write data from or into any of the plurality of logical blocks constructed. The logical blocks are management units in which any of the physical blocks is grouped across the plurality of channels. The controller is configured to construct the plurality of logical blocks so that a first number of defective blocks and a second number of pseudo defective blocks for shortfall defective blocks with respect to a target number of defective blocks are distributed into the plurality of logical blocks.Type: GrantFiled: December 9, 2021Date of Patent: July 4, 2023Assignee: Kioxia CorporationInventor: Akira Shimizu
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Patent number: 11687263Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a request from a requester for a superblock, determine that one or more blocks of a die of the superblock are expected to fail, and either replace the one or more blocks of the die with another one or more blocks from a different die or add the another one or more blocks from the different die and disable the one or more blocks of the die, and provide the superblock to the requester. The superblock provided to the requester is erased prior to the providing and is the same size as an original superblock.Type: GrantFiled: December 1, 2021Date of Patent: June 27, 2023Assignee: Western Digital Technologies, Inc.Inventors: Vineet Agarwal, Chaitanya Kavirayani, Ratanvel Nadar
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Patent number: 11681475Abstract: Techniques for processing an access request and updating a storage system are provided. For instance, a method comprises: receiving an access request for an object associated with a storage system, the storage system including a plurality of physical nodes, each of the plurality of physical nodes including at least one set of virtual units, each set of virtual units including at least one virtual unit; determining, from a plurality of sets of virtual units included in the plurality of physical nodes of the storage system, a target set of virtual units associated with the object; and determining, from the target set of virtual units, a target virtual unit corresponding to the object. With the technical solution of the present disclosure, not only a set of virtual units on a physical node may be easily split and merged, but also huge computing resources that need to be allocated may be saved, so better user experience may be brought about at a lower cost.Type: GrantFiled: February 4, 2022Date of Patent: June 20, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Lu Lei, Ao Sun
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Patent number: 11681469Abstract: The disclosed embodiments are related to storing critical data in a memory device such as Flash memory device. In one embodiment, a method performed by a controller of a memory device comprises receiving a critical operation from a host processor, the critical operation accessing a memory array; retrieving a temperature value of the memory array from a temperature sensor; and conditionally processing the critical operation based on the temperature value.Type: GrantFiled: February 22, 2021Date of Patent: June 20, 2023Assignee: Micron Technology, Inc.Inventor: Gil Golov
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Patent number: 11640253Abstract: A data storage device includes a non-volatile memory (NVM) device and a controller coupled to the NVM device. The controller is configured to create a bad block table that tracks bad blocks of the NVM device, send the bad block table to a host memory location, and check the bad block table to determine whether a block to be read or written to is bad. The controller is further configured to request information on a bad block from the bad block table located in the host memory location, determine that the requested information is not available from the host memory location, and retrieve the requested information from a location separate from the host memory location. A sum of the times to generate a request to check the flat relink table, execute the request, and retrieve the requested information is less than a time to process a host command.Type: GrantFiled: June 1, 2021Date of Patent: May 2, 2023Assignee: Western Digital Technologies, Inc.Inventors: Karin Inbar, David Haliva, Gadi Vishne
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Patent number: 11625178Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having improved zone recovery speed may include a memory device including a plurality of memory blocks, and a memory controller configured to, in response to the zone open request, allocate memory blocks to store data of a logical address group corresponding to an open-requested zone among the plurality of memory blocks, and control the memory device to store zone recovery information included in a zone open request, and wherein the zone recovery information indicates whether data to be stored in the open-requested zone is to be recovered in a next power cycle.Type: GrantFiled: May 21, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventor: Eu Joon Byun
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Patent number: 11625171Abstract: A method, system and apparatus for protecting from out of bounds memory references, including establishing a threshold number of active objects for examination for an out of bounds memory reference, determining whether a number of active objects for an application exceeds the threshold, and when the number of active objects exceeds the threshold, storing at least part of information about the active objects in an overflow table in a memory.Type: GrantFiled: September 16, 2021Date of Patent: April 11, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Richard H. Boivie, Tong Chen, Alper Buyuktosunoglu, Benjamin P Segal
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Patent number: 11609849Abstract: Examples may include a deduplication system threshold based on an amount of wear of a storage device. Examples may obtain an indication of an amount of wear experienced by at least one storage device storing a plurality of container indexes of a deduplication system, and may adjust a threshold of the deduplication system based on the amount of wear.Type: GrantFiled: April 30, 2021Date of Patent: March 21, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: John Butt, Dave Donaghy, Mayuri Jain, Alastair Slater
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Patent number: 11604738Abstract: A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in the metadata cache memory, store, in the data cache memory, each portion of compressed data having a selected portion of corresponding metadata stored in the metadata cache memory. Each portion of compressed data, having the selected portion of corresponding metadata stored in the metadata cache memory, is decompressed.Type: GrantFiled: September 28, 2018Date of Patent: March 14, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Shomit N. Das, Matthew Tomei, David A. Wood
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Data storage device and method for preventing accidental updates and deletions using data versioning
Patent number: 11592995Abstract: A data storage device and method for preventing accidental updates and deletions using data versioning are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to: receive a command from a host to modify data stored in the memory, wherein the data is associated with a host identifier created by the data storage device; determine whether the host is associated with the host identifier; in response to determining that the host is associated with the host identifier, modify the data; and in response to determining that the host is not associated with the host identifier, create a new version of the data without modifying the data. Other embodiments are provided.Type: GrantFiled: April 19, 2021Date of Patent: February 28, 2023Assignee: Western Digital Technologies, Inc.Inventors: Niraj Srimal, Ramanathan Muthiah