Patents Examined by Dustin Bone
  • Patent number: 9268486
    Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: February 23, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Uchigaito, Kenzo Kurotsuchi, Seiji Miura
  • Patent number: 9256536
    Abstract: A method and apparatus for providing shared caches. A cache memory system may be operated in a first mode or a second mode. When the cache memory system is operated in the first mode, a first cache and a second cache of the cache memory system may be operated independently. When the cache memory system is operated in the second mode, the first cache and the second cache may be shared. In the second mode, at least one bit may overlap tag bits and set index bits among bits of a memory address.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: February 9, 2016
    Assignees: Samsung Electronics Co., Ltd., INDUSTRY-ACADEMIA COOPERATION GROUP OF SEJONG UNIVERSITY
    Inventors: Jeong Ae Park, Sang Oak Woo, Seok Yoon Jung, Young sik Kim, Woo Chan Park
  • Patent number: 9235511
    Abstract: Embodiments relate to methods, computer systems and computer program products for improving software performance by identifying and preloading data pages. Embodiments include executing an instruction that requests a data page from the one or more auxiliary storage devices. Based on determining that the instruction is present in the long-running instruction list, embodiments include examining one or more characteristics of a plurality of data pages that will be requested by the instruction. Based on determining that the plurality of data pages are located on a single auxiliary storage device and that the plurality of data pages can be efficiently retrieved by the single auxiliary storage device, embodiments include initiating a pre-load operation to move the plurality of data pages to the main memory.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas F. Rankin, Elpida Tzortzatos
  • Patent number: 9235516
    Abstract: Described are techniques for processing data operations. A read request for first data is received at a data storage system. It is determined whether the read request results in a cache hit whereby the first data is stored in a cache of the data storage system, or whether the read request otherwise results in a cache miss. If the read request results in a cache miss, processing is performed to determine determining whether to perform cacheless read processing or deferred caching processing to service the read request. Determining whether to perform cacheless read processing or deferred caching processing is performed in accordance with criteria including a measurement indicating a level of busyness of a back-end component used to retrieve from physical storage any portion of the first data not currently stored in the cache.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: January 12, 2016
    Assignee: EMC Corporation
    Inventors: Marik Marshak, Dan Aharoni, Stephen Richard Ives, Amnon Naamad, Peng Yin, Ningdong Li, Sanjay Narahari, Manickavasasaham M. Senghuden, Jeffrey Wilson
  • Patent number: 9176854
    Abstract: Presenting enclosure cache as local cache in an enclosure attached server, including: determining, by the enclosure, a cache hit rate for local server cache in each of a plurality of enclosure attached servers; determining, by the enclosure, an amount of available enclosure cache for use by one or more of the enclosure attached servers; and offering, by the enclosure, some portion of the available enclosure cache to an enclosure attached server in dependence upon the cache hit rate and the amount of available enclosure cache.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 3, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Lydia M. Do, Christopher J. Hardee, Adam Roberts
  • Patent number: 9158669
    Abstract: Presenting enclosure cache as local cache in an enclosure attached server, including: determining, by the enclosure, a cache hit rate for local server cache in each of a plurality of enclosure attached servers; determining, by the enclosure, an amount of available enclosure cache for use by one or more of the enclosure attached servers; and offering, by the enclosure, some portion of the available enclosure cache to an enclosure attached server in dependence upon the cache hit rate and the amount of available enclosure cache.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 13, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Gary D. Cudak, Lydia M. Do, Christopher J. Hardee, Adam Roberts
  • Patent number: 9152328
    Abstract: Methods and structure for automatic creation of Redundant Array of Independent Disks (RAID) volumes are provided. The system comprises A RAID controller that includes a memory and a processor. The memory stores information describing storage devices of a storage system. The processor is able to receive a request to generate a RAID volume, to access the memory to identify a first group of storage devices that each have a first storage capacity, and to determine an expected size of a volume implemented by the first group. The processor is further able to access the memory to identify a second group of storage devices that each have a second storage capacity, to determine an expected size of a volume implemented by the first group and the second group, and to select one or more of the groups to create the requested volume based on the expected sizes.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: October 6, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd
    Inventors: Jianning Wang, Daniel G. Samuelraj, Subhankar Mukherjee
  • Patent number: 9142272
    Abstract: Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Gary A. Van Huben, Patrick J. Meaney, John S. Dodson, Scot H. Rider, James C. Gregerson, Eric E. Retter, Irving G. Baysah, Glenn D. Gilda, Lawrence D. Curley, Vesselina K. Papazova
  • Patent number: 9141531
    Abstract: A disk drive having a disk, a head actuated over the disk, a volatile semiconductor memory (VSM), a command queue, and control circuitry operable to receive a plurality of write commands from a host, store the plurality of write commands in the command queue, store write data for the plurality of write commands in the VSM, and flush, from the VSM to the disk, a portion of the write data corresponding to a predetermined number of tracks.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 22, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Aznizam Abdullah Salehudin, Kai Ling Lee
  • Patent number: 9141543
    Abstract: Systems and methods for writing data from a caching agent to a main memory in a computer system are provided. In systems and methods for writing data from a caching agent to a main memory in a computer system, a notice of an occurrence of a triggering event is received. In response to the receipt of the notice, data is retrieved from a storage array of the caching agent in accordance with a pre-clean criterion. The pre-clean criterion identifies the data that is being retrieved from the storage array prior to receiving a command on the data. The data is written to the main memory, where the writing of the data causes a memory address associated with the data to have identical contents in the storage array and in the main memory.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 22, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Kim Schuttenberg, R. Frank O'Bleness
  • Patent number: 9116737
    Abstract: A framework for converting between copy-on-write (COW) and redo-based technologies is disclosed. To take a virtual disk snapshot, disk descriptor files, which include metadata information about data stored in virtual volumes (vvols), are “swizzled” such that the descriptor file for a latest redo log, to which IOs are currently performed, points to the base vvol of a COW-based vvol hierarchy. A disk descriptor file previously associated with the base vvol may also be updated to point to the vvol newly created by the snapshot operation. To revert to an earlier disk state, a snapshot may be taken before copying contents of a snapshot vvol of the COW-based vvol hierarchy to a base vvol of the hierarchy, thereby ensuring that the reversion can be rolled back if it is unsuccessful. Reference counting is performed to ensure that vvols in the vvol hierarchy are not orphaned in delete and revert use cases.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: August 25, 2015
    Assignee: VMware, Inc.
    Inventors: Tejasvi Aswathanarayana, Komal Desai, Patrick William Penzias Dirks, Sujay Godbole, Jesse Pool, Ilia Sokolinski, Derek Uluski
  • Patent number: 9099171
    Abstract: An information processor includes an information processing sub-system having information processing circuits and a memory sub-system performing data communication with the information processing sub-systems, wherein the memory sub-system has a first memory, a second memory, a third memory having reading and writing latencies longer than those of the first memory and the second memory, and a memory controller for controlling data transfer among the first memory, the second memory and the third memory; graph data is stored in the third memory; the memory controller analyzes data blocks serving as part of the graph data, and performs preloading operation repeatedly to transfer the data blocks to be required next for the execution of the processing from the third memory to the first memory or the second memory on the basis of the result of the analysis.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: August 4, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Uchigaito, Kenzo Kurotsuchi, Seiji Miura
  • Patent number: 9047173
    Abstract: A method, an apparatus, and a non-transitory computer readable medium for tracking prefetches generated by a stride prefetcher are presented. Responsive to a prefetcher table entry for an address stream locking on a stride, prefetch suppression logic is updated and prefetches from the prefetcher table entry are suppressed when suppression is enabled for that prefetcher table entry. A stride is a difference between consecutive addresses in the address stream. A prefetch request is issued from the prefetcher table entry when suppression is not enabled for that prefetcher table entry.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: June 2, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alok Garg, Sharad Bade, John Kalamatianos
  • Patent number: 8077871
    Abstract: A content processing apparatus includes a read unit which reads encrypted key information from a recording medium, a decryption unit which decrypts the encrypted key information with a device key and dynamic information to obtain key information containing content keys, an update unit which updates the dynamic information, a key information processing unit which updates the key information by extracting a content key corresponding to a move target content from the key information, and removing the content key from the key information, a first encryption unit which encrypts the updated key information with the device key and the updated dynamic information, a second encryption unit which encrypts the content key with a shared key, and a write unit which overwrites the updated encrypted key information on the encrypted key information in the medium and writes the encrypted content key in the medium.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Taku Kato
  • Patent number: 7979896
    Abstract: A web service includes a protected resource. A requester requests access to the protected resource by sending a request to the web service. The web service prevents access to the web service until the request has been authorized by an authorizer. After the request has been authorized by the authorizer, the web service allows the requester to access the protected resource.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: July 12, 2011
    Assignee: Microsoft Corporation
    Inventors: Craig V. McMurtry, Alexander T. Weinert, Vadim Meleshuk, Mark E. Gabarra