Abstract: A display device includes a first polyimide layer, a first silicon oxide layer located above and in direct contact with the first polyimide layer, an amorphous silicon layer located above and in direct contact with the first silicon oxide layer, a second polyimide layer located above and in direct contact with the amorphous silicon layer, a plurality of light-emitting elements located above the second polyimide layer, a transistor array located above the second polyimide layer, the transistor array being configured to control light emission of the plurality of light-emitting elements, a transparent conductive layer located between the transistor array and the second polyimide layer, and a second silicon oxide layer located between and in direct contact with the transparent conductive layer and the second polyimide layer.

Abstract: An organic light emitting device having a structure that a plurality of light emitting units are deposited, is disclosed, of which white color shift caused by variation of a viewing angle is reduced through a combination between dopant materials of the respective light emitting units. The organic light emitting device includes dopant materials emitting light of different wavelengths from the plurality of light emitting units. Therefore, in the organic light emitting device, variation of color and luminance, which is perceived by a user as a viewing angle is varied, may be reduced.

Abstract: A transparent display panel and a transparent display device including the same are disclosed. In a transparent display panel, a VSS voltage line does not surround an outer periphery of a display region. Rather, upper and lower VSS voltage lines respectively disposed on upper and lower sides to the display region are electrically connected to each other via at least one VSS voltage connection line extending across the display region. Thus, left and right non-transparent and thick VSS voltage lines disposed on the left and right sides to the display region may be omitted. Thus, a transparent region of the transparent display panel and a bezel of a transparent display device may be increased or maximized or the bezel thereof may be made slim.

Abstract: The present disclosure relates to a display substrate, a method for preparing the same, and a display device. The display substrate of the present disclosure includes a base substrate, a pixel definition layer located on the base substrate, and a first pixel and a second pixel that are adjacent to each other and defined by the pixel definition layer, in which a spacer function layer for blocking hole transport between adjacent pixels is arranged at at least a part of a contact interface between the second hole transport layer in the second pixel and the light function layer in the first pixel. By providing the spacer function layer, the present disclosure effectively prevents the migration of holes between the hole transport layers of adjacent pixels or between the hole transport layer and the light emitting layer, thereby avoiding accompanying light emission between adjacent pixels.

Abstract: A SEU tolerant structure has two logic sections that generate two output signals that are complementary such that a fault which affects one section cannot affect the other section. Adjacent NMOS regions or adjacent PMOS regions contain no logic inversions in the combinational logic or if logic inversions in the combinational logic are present where all gates following the inversion are SEU hard by design. The circuits can be realized using one of a Complex CMOS gate, pass transistor logic, Multiplexor logic, AND-OR logic or OR-AND logic.

Abstract: An organic electroluminescence device includes two or more emitting units disposed between an anode and a cathode, and an intermediate layer, in which the intermediate layer contains a phenanthroline compound, the laminated emitting unit includes a first emitting layer containing a first host material and a second emitting layer containing a second host material, and a triplet energy T1(H1) of the first host material and a triplet energy T1(H2) of the second host material satisfy a relationship of a numerical formula (Numerical Formula 3), T1(H1)>T1(H2)??(Numerical Formula 3).

Abstract: A display panel, a display device, and a method for manufacturing a display panel are disclosed. The display panel includes a first power bus and a first power line. A display region of the display panel includes a first region and a second region, the first region and the second region include a plurality of first pixel units, respectively, the first power bus is between the first region and the second region, and the first power line is electrically connected to the first power bus and extends from the first power bus to the first region and the second region, respectively, so as to supply power to the plurality of first pixel units in the first region and the second region, respectively.

Abstract: The present disclosure provides an organic light emitting diode (OLED) substrate and a manufacturing method thereof, and a display device. The OLED substrate includes: a base substrate; a pixel defining layer on the base substrate, the pixel defining layer including pixel defining patterns for defining sub-pixel units, each sub-pixel unit being defined between adjacent two of the pixel defining patterns; and an organic light emitting layer on a side of the pixel defining layer away from the base substrate, the organic light emitting layer including a first portion in each sub-pixel unit and a second portion on each pixel defining pattern. Each pixel defining pattern is provided with a groove structure therein, and part of the second portion of the organic light emitting layer in the groove structure and the other part of the second portion of the organic light emitting layer are spaced apart from each other.

Abstract: The present disclosure is related to an array substrate. The array substrate may include a base substrate; a plurality or light-emitting devices on the base substrate; a photosensitive device between the light-emitting devices and the base substrate; and a refractive layer between the photosensitive device and the light-emitting devices. The refractive layer may be at a distance from the photosensitive device, and the refractive layer may cover at least a gap region between the adjacent light-emitting devices. A refractive index of the refractive layer may be larger than a refractive index of a film layer in the gap region between the refractive layer and the photosensitive device, and an orthographic protection of the photosensitive device on the base substrate may at least partially overlap an orthographic projection of the light-emitting devices on base substrate.

Abstract: Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

Abstract: A display panel includes a base layer, a first thin film transistor on the base layer, a second thin film transistor electrically coupled to the first thin film transistor, and a light emitting element electrically coupled to the second thin film transistor. The first thin film transistor includes a first semiconductor pattern on the base layer, a first barrier pattern on the first semiconductor pattern and including a gallium (Ga) oxide and a zinc (Zn) oxide, and a first control electrode on the first barrier pattern and overlapping the first semiconductor pattern. Accordingly, a signal transmission speed of the display panel may be improved, and electrical characteristics and reliability of the thin film transistor included in the display panel may be improved.

Abstract: A method of manufacturing a display panel includes providing a base substrate and forming a plurality of anodes above the base substrate; forming a photoresist layer above a side of the base substrate above which the plurality of anodes are formed, the photoresist layer including a plurality of openings and each opening corresponding to at least one anode; and forming a plurality of light emitting layers and a cathode layer sequentially above a side of the base substrate above which the plurality of anodes and the photoresist layer are formed, the cathode layer including a plurality of cathode films and each cathode film corresponding to a single opening.

Abstract: The present invention provides a double-sided display device and a manufacturing method thereof. The double-sided display includes an array substrate, an organic light-emitting functional layer, and a semi-transparent semi-reflective electrode arranged in sequence, and a liquid crystal cell disposed on a side of the semi-transparent semi-reflective electrode close to the organic light-emitting functional layer. One part of light emitted by the organic light-emitting functional layer penetrates through the semi-transparent semi-reflective electrode to display on one side of the double-sided display device, and the other part of the light is reflected toward the liquid crystal unit by the semi-transparent semi-reflective electrode to display on the other side of the double-sided display.

Abstract: A display device includes a base substrate including a display area and a non-display area around the display area are defined, a first interlayer insulating layer disposed on the base substrate, a second interlayer insulating layer disposed on the first interlayer insulating layer, a first semiconductor layer disposed on the second interlayer insulating layer and including an oxide, and a first gate insulating layer disposed on the first semiconductor layer, wherein the material of the first interlayer insulating layer and the material of the second interlayer insulating layer are different from each other. Methods of manufacturing a display device are also disclosed.

Abstract: A display panel, a display device, and a manufacturing method of the display panel are disclosed. The display panel includes an array substrate and a light-emitting function layer disposed on the array substrate. The display panel includes a display area and a sensor light-receiving area adjacent to the display area. The array substrate includes a thin film transistor array disposed in the display area, the light-emitting function layer is disposed in the display area and the sensor light-receiving area, and the thin film transistor array is electrically connected to the light-emitting function layer.

Abstract: The present disclosure provides a method for preparing a semiconductor device. The semiconductor device includes a substrate, a first region, a second region, a third region, a fourth region, a fifth region and a sixth region. The first type region is disposed on the substrate and has a ring structure. The second type region is disposed on the substrate and disposed in the center of the first type region. A plurality of second well regions are formed in the first region, the second region, the fourth region, the fifth region and the sixth region. A plurality of second well regions in the first region, the second region, the fourth region, the fifth region and the sixth region. The first well region, the second well region, the first type region and the second type region are formed by ion implantation.

Abstract: Disclosed are a display module and a display apparatus. The display module includes a first display region and a second display region bordering the first display region. The first display region includes first pixel circuit regions arranged in an array and multiple photosensitive regions. The second display region includes second pixel circuit regions arranged in an array. The number of first pixel circuit regions per unit area is equal to and the number of second pixel circuit regions per unit area. The display module further includes an image acquisition module, which includes a micro-lens module. The micro-lens module includes multiple micro-lenses in one-to-one correspondence with the multiple photosensitive regions, and each micro-lens is disposed in a corresponding photosensitive region.

Abstract: A virtual image display device including a display panel including a plurality of pixels and configured to display an image, a window disposed on the display panel, and a multi-viewpoint layer provided between the display panel and the window, and including a plurality of lenses.

Abstract: A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower groove is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper groove is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper grooves. A luminescent device is disposed on the organic layer and overlaps the first region.

Abstract: Embodiments of three-dimensional (3D) memory devices having a shielding layer and methods for forming the 3D memory devices are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral device is formed on a substrate. A first interconnect layer including a first plurality of interconnects is formed above the peripheral device. A shielding layer including a conduction region is formed above the first interconnect layer. A second interconnect layer including a second plurality of interconnects is formed above the shielding layer. The conduction region of the shielding layer covers an area of the first and second plurality of interconnects in the first and second interconnect layers. A plurality of memory strings each extending vertically above the second interconnect layer are formed.