Abstract: A semiconductor device includes a lower wiring, an upper wiring on the lower wiring, and a via between the lower wiring and the upper wiring. The lower wiring has a first end surface and a second end surface opposing each other, the upper wiring has a third end surface and a fourth end surface opposing each other, and the via has a first side adjacent to the second end surface of the lower wiring and a second side adjacent to the third end surface of the upper wiring. A distance between a lower end of the first side of the via and an upper end of the second end surface of the lower wiring is less than ? of a width of a top surface of the via, and a distance between an upper end of the second side of the via and an upper end of the third end surface of the upper wiring is less than ? of the width of the top surface of the via.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction; a gate structure extending across the fin-type active region in a second direction, different from the first direction; a source/drain region in the fin-type active region on one side of the gate structure; and first and second contact structures connected to the source/drain region and the gate structure, respectively, wherein at least one of the first and second contact structures includes a seeding layer on at least one of the gate structure and the source/drain region and including a first crystalline metal, and a contact plug on the seeding layer and including a second crystalline metal different from the first crystalline metal, and the second crystalline metal is substantially lattice-matched to the first crystalline metal at an interface between the seeding layer and the contact plug.

Abstract: A method for manufacturing a compound semiconductor substrate that can achieve thinning of SiC film, wherein the method includes forming a SiC film on one principal surface side of a Si substrate and forming a recessed part in which a bottom surface is Si in a central part of another principal surface of the Si substrate.

Abstract: The present disclosure provides a solar cell. The solar cell includes a substrate, where the substrate has a front surface and a rear surface, the rear surface includes a textured region and a flat region, a doped surface field is formed in the textured region of the substrate; a tunneling dielectric layer, where the tunneling dielectric layer is located on the flat region; a doped conductive layer, where the doped conductive layer is located on the tunnelling dielectric layer, the doped conductive layer has doping elements, and the doped conductive layer has the same type of the doping elements with the doped surface field; a rear electrode, where a part of a bottom surface of the rear electrode is located in the doped conductive layer and the part of the bottom surface of the rear electrode is in contact with the doped surface field.

Abstract: Disclosed herein are compositions, methods and devices that allow for water-soluble epitaxial lift-off of III-V. Epitaxial growth of STO/SAO templates on STO (001) and Ge (001) substrates were demonstrated. Partially epitaxial GaAs growth was achieved on STO/SAO/STO substrate templates.

Abstract: A photodetector based on PtSe2 and a silicon nanopillar array includes a PMMA light-transmitting protective layer, a graphene transparent top electrode, a silicon nanopillar array structure coated with few-layer PtSe2, and metal electrodes of the graphene transparent top electrode and the silicon nanopillar array structure. A method for preparing the photodetector includes steps of: preparing graphene with a CVD method; preparing a silicon nanopillar array structure through dry etching; coating few-layer PtSe2 on surfaces of the silicon nano-pillar array structure through laser interference enhanced induction CVD; preparing graphene transparent top electrode; and magnetron-sputtering metal electrodes. The photodetector prepared by the present invention has a detection range from visible light to near-infrared wavebands. The silicon nanopillar array structure enhances light absorption of the detector, so that the detector has high sensitivity, simple structure and strong practicability.

Abstract: A semiconductor storage device includes a logic circuit formed on a substrate, a first area formed on the logic circuit and has a plurality of first insulating layers and a plurality of conductive layers alternately stacked in a first direction, a plurality of memory pillars MP which extend in the first area in the first direction, a second area which is formed on the logic circuit and has the plurality of first insulating layers 33 and a plurality of second insulating layers alternately stacked in the first direction, and a contact plug CP1 which extends in the second area in the first direction and is connected to the logic circuit.

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Abstract: A method of generating a germanium structure includes performing an epitaxial depositing process on an assembly of a silicon substrate and an oxide layer, wherein one or more trenches in the oxide layer expose surface portions of the silicon substrate. The epitaxial depositing process includes depositing germanium onto the assembly during a first phase, performing an etch process during a second phase following the first phase in order to remove germanium from the oxide layer, and repeating the first and second phases. A germanium crystal is grown in the trench or trenches. An optical device includes a light-incidence surface formed by a raw textured surface of a germanium structure obtained by an epitaxial depositing process without processing the surface of the germanium structure after the epitaxial process.

Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

Abstract: An optical sensor includes a graphene layer, a first electrode and a second electrode that are connected to the graphene layer, and an enhancement layer. The enhancement layer is disposed below the graphene layer to enhance the intensity of an optical electric field by surface plasmon resonance. The first electrode and the second electrode are arranged parallel to a first direction. The intensity of the optical electric field enhanced by the enhancement layer is greater on a first electrode side than on a second electrode side with respect to a centerline in the first direction of the graphene layer.

Abstract: A semiconductor memory structure includes a fin structure formed over a substrate. The structure also includes a gate structure formed across the fin structure. The structure also includes spacers formed over opposite sides of the gate structure. The structure also includes source drain epitaxial structures formed on opposite sides of the gate structure beside the spacers. The gate structure includes a III-V ferroelectric layer formed between an interfacial layer and a gate electrode layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

Abstract: A transistor, integrated semiconductor device and methods of making are provided. The transistor includes a dielectric layer having a plurality of dielectric protrusions, a channel layer conformally covering the protrusions of the dielectric layer to form a plurality of trenches between two adjacent dielectric protrusion, a gate layer disposed on the channel layer. The gate layer 106 has a plurality of gate protrusions fitted into the trenches. The transistor also includes active regions aside the gate layer. The active regions are electrically connected to the channel layer.

Abstract: A vertical type transistor includes: a substrate; a first source/drain electrode layer provided on the substrate; a second source/drain electrode layer provided above the first source/drain electrode layer; a first gate electrode layer provided between the first and second source/drain electrode layers; a first gate insulating film passing through the first gate electrode layer; a hole passing through the second source/drain electrode layer, the first gate insulating film, and the first source/drain electrode layer; and a first channel layer provided on a lateral side of the hole, wherein the first channel layer may include a 2D semiconductor.

Abstract: Integrated circuit structures having source or drain structures with phosphorous and arsenic co-dopants are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The first and second source or drain structures include silicon, phosphorous and arsenic, with an atomic concentration of phosphorous substantially the same as an atomic concentration of arsenic.

Abstract: A photosensor device includes a substrate, a graphene layer provided on the substrate, a pair of electrodes electrically connected to the graphene layer, and a passivation layer formed of a resin and configured to cover the graphene layer. The graphene layer has holes which are periodically arranged, and the passivation layer is provided with openings that communicate with the holes. The side surfaces of the holes and the inner walls of the openings are continuously covered with an insulating thin film.

Abstract: In some embodiments, a pixel sensor is provided. The pixel sensor includes a first photodetector arranged in a semiconductor substrate. A second photodetector is arranged in the semiconductor substrate, where a first substantially straight line axis intersects a center point of the first photodetector and a center point of the second photodetector. A floating diffusion node is arranged in the semiconductor substrate at a point that is a substantially equal distance from the first photodetector and the second photodetector. A pick-up well contact region is arranged in the semiconductor substrate, where a second substantially straight line axis that is substantially perpendicular to the first substantially straight line axis intersects a center point of the floating diffusion node and a center point of the pick-up well contact region.

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.