Patents Examined by Earl N. Taylor
  • Patent number: 10634958
    Abstract: Provided is a manufacturing method of a black photo spacer array substrate. In a manufacturing method of a black photo spacer array substrate, a double layer color resist structure formed with a first color resist layer and a second color resist layer is used to pad a main pad part and a sub pad part of a main photo spacer and a sub photo spacer. Then, a thickness of the main photo spacer and a thickness of the sub photo spacer are decreased to reduce the usage amount of black photo spacer material of forming the main photo spacer and the sub photo spacer to reduce the production cost. A height difference of the main photo spacer and the sub photo spacer can be achieved by decreasing a thickness of the first color resist layer under the sub pad part with a half exposure process.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 28, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Zhuming Deng
  • Patent number: 10636822
    Abstract: In a photoelectric-conversion element having a large light receiving region for a high-speed transfer, and a solid-state image sensor including the photoelectric-conversion element, the photoelectric-conversion element includes first to eighth charge read-out regions, which are provided at positions symmetric with respect to a center position of a light receiving region and first to eighth field-control electrodes, which are arranged on both sides of charge-transport paths extending from the center position of the light receiving region to the first to eighth charge read-out regions, respectively, and change depletion potentials of the charge-transport paths and the octuple charge-transfer channels.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 28, 2020
    Assignee: National University Corporation Shizuoka University
    Inventors: Shoji Kawahito, Min-Woong Seo, Keita Yasutomi, Yuya Shirakawa
  • Patent number: 10629546
    Abstract: A semiconductor device including a substrate including a central region and a peripheral region surrounding the central region, a semiconductor integrated circuit in the central region, and a three-dimensional crack detection structure in the peripheral region, the three-dimensional crack detection structure surrounding the central region, the three-dimensional crack detection structure including a first pattern, a second pattern, and a third pattern, the first and second patterns extending in a first direction and spaced apart from each other, the third pattern being parallel to an upper surface of the substrate and connecting the first and second patterns to each other, the third pattern including a first portion and a second portion, the first and second portions extending in a second direction and a third direction respectively, the second direction intersecting with the first direction, the third direction intersecting with the first and second directions may be provided.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: April 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jung Hyun Roh
  • Patent number: 10620492
    Abstract: The present disclosure relates to a method for manufacturing an array substrate, an array substrate and a display device. The method includes: disposing, on a substrate, a plurality of thin film transistors arranged in an array; depositing a first transparent electrode layer on the substrate and processing the first transparent electrode layer by using a first pattern process, so as to form a plurality of first electrodes connected with drains of the film transistors, and a connecting electrode connecting adjacent ones of the first electrodes; disposing a functional structure on a side of the first transparent electrode layer that is away from the substrate; and processing the connecting electrode by using a second pattern process and disconnecting the connecting electrode, so as to form a convex connection on an edge of the first electrode.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 14, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Su, Xiaofei Yang, Xu Liu, Xinghua Li
  • Patent number: 10622579
    Abstract: An organic lighting-emitting diode (OLED) display panel, a backplane attaching method and a backplane attaching device are provided. The OLED display panel includes: a flexible substrate, and a thin film transistor layer and a light-emitting layer prepared on the flexible substrate. The flexible substrate includes a first flexible substrate layer, a fixing layer and a second flexible substrate layer sequentially stacked one another. The fixing layer includes an organic film layer and magnetic particles embedded in the organic film layer. The magnetic particles are located in an internal of the flexible substrate.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: April 14, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Panfei Bao
  • Patent number: 10622282
    Abstract: An apparatus for cooling an electronic device is disclosed. In an aspect, the apparatus includes a vapor chamber coupled to a heat generating component of the electronic device. In an aspect, the vapor chamber is coupled to an inner surface of an outer cover of the electronic device and conforms to a shape of the inner surface of the outer cover. In another aspect, the vapor chamber forms the outer cover of the electronic device. The vapor chamber comprises a sealed container, a wick structure disposed on an inner surface of the sealed container, and a fluid contained in the sealed container, wherein as heat is applied to an evaporator side of the sealed container coupled to the heat generating component, the fluid vaporizes over a condenser side of the sealed container opposite the evaporator side and returns to the evaporator side via the wick structure.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: April 14, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Rupal Prajapati, Shujuan Wang, Peng Wang
  • Patent number: 10608096
    Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a source region and a drain region within a substrate, forming spacers in direct contact with sidewalls of a sacrificial layer, depositing an inter-layer dielectric (ILD) over the source and drain regions, replacing the sacrificial layer with a gate structure, removing the ILD, and depositing a sacrificial dielectric layer. The method further includes removing portions of the sacrificial dielectric layer to expose top surfaces of the source and drain regions, depositing a conductive material over the exposed top surfaces of the source and drain regions, and removing remaining portions of the sacrificial dielectric layer to form air gap spacers between the gate structure and the source and drain regions.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, Choonghyun Lee, Heng Wu
  • Patent number: 10598802
    Abstract: Among other things, a detector unit for a radiation detector array is provided. The detector unit includes a radiation detection sub-assembly including a scintillator and a photodetector array. A first routing layer is coupled to the photodetector array of the radiation detection sub-assembly at a first surface of the routing layer. An electronics assembly includes an analog-to-digital converter that converts an analog signal to a digital signal. A second routing layer is disposed between the A/D converter and the first routing layer. A shielding element is disposed between the A/D converter and the second routing layer. The shielding element shields the A/D converter from the radiation photons. The second routing layer couples the electronics sub-assembly to the first routing layer. A first coupling element couples the A/D converter to the second routing layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: March 24, 2020
    Assignee: Analogic Corporation
    Inventors: Randy Luhta, Chris Vrettos
  • Patent number: 10600705
    Abstract: An electronic switching element includes at least one semiconductor switch inserted into a layer sequence of a conductor structure element; and at least two busbars which are configured to contact-connect the at least one semiconductor switch, wherein the at least two busbars run substantially above one another in the layer sequence of the conductor structure element.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 24, 2020
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle, Rainer Jäackle
  • Patent number: 10600726
    Abstract: A leadframe includes first and second surfaces, a plurality of leads, and a hole-defining wall unit including a plurality of first-hole defining walls each defining a first through hole and a plurality of second-hole defining walls each defining a second through hole. Each of the first and second through holes is formed between two adjacent ones of the leads. Each of the first hole-defining walls has top and bottom edges respectively forming arcuate and burr regions with the first and surfaces at junctions therebetween. Each of the second hole-defining walls has top and bottom edges respectively forming burr and arcuate regions with the first and second surfaces at junctions therebetween.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 24, 2020
    Assignee: CHANG WAH TECHNOLOGY CO., LTD.
    Inventor: Chia-Neng Huang
  • Patent number: 10593721
    Abstract: In pixels that are two-dimensionally arranged in a matrix fashion in the pixel array unit of a solid-state imaging element, a photoelectric conversion film having a light shielding film buried therein is formed and stacked on the light incident side of the photodiode. The present technique can be applied to a CMOS image sensor compatible with the global shutter system, for example.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 17, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kenichi Nishizawa
  • Patent number: 10586864
    Abstract: A vertical transistor and a method of creating thereof are provided. A substrate is provided. A first electrode, comprising a two-dimensional (2D) material, is defined on top of the substrate. A spacer is deposited on top of the first electrode. A second electrode, comprising a 2D material, is defined on top of the spacer. A mask layer is formed on top of the second electrode. A channel is formed on top of the mask layer. A gate dielectric layer is provided on top of the channel. A gate coupled to the second portion of the gate dielectric is provided.
    Type: Grant
    Filed: August 5, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, Qing Cao
  • Patent number: 10580861
    Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 3, 2020
    Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.
    Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
  • Patent number: 10580916
    Abstract: An infrared detector includes, a substrate, a lower contact layer formed on the substrate, a first light receiving layer that is formed on the lower contact layer and has a quantum well structure, an intermediate contact layer formed on the first light receiving layer, a second light receiving layer that is formed on the intermediate contact layer and has a quantum well structure, and an upper contact layer formed on the second light receiving layer. Each of the first light receiving layer and the second light receiving layer includes, a first semiconductor layer that is doped with a first conductivity-type impurity, and a second semiconductor layer that is formed on the first semiconductor layer, and is doped with a second conductivity-type impurity which compensates the first conductivity-type impurity.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Ryo Suzuki
  • Patent number: 10573521
    Abstract: A method of forming gate structures to a nanosheet device that includes forming at least two stacks of nanosheets, wherein each nanosheet includes a channel region portion having a gate dielectric layer present thereon. The method may further include forming a dual metal layer scheme on the gate dielectric layer of each nanosheet. The dual metal layer scheme including an etch stop layer of a first composition and a work function adjusting layer of a second composition, wherein the etch stop layer has a composition that provides that the work function adjusting layer is removable by a wet etch chemistry that is selective to the etch stop layer.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junli Wang, Alexander Reznicek, Shogo Mochizuki, Joshua Rubin
  • Patent number: 10559623
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Patent number: 10559617
    Abstract: Embodiments of the invention include a semiconductor light emitting device including a semiconductor structure. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. A wavelength converting structure is disposed in a path of light emitted by the light emitting layer. A diffuse reflector is disposed along a sidewall of the semiconductor light emitting device and the wavelength converting structure. The diffuse reflector includes a pigment. A reflective layer is disposed between the diffuse reflector and the semiconductor structure. The reflective layer is a different material from the diffuse reflector.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: February 11, 2020
    Assignee: LUMILEDS LLC
    Inventors: Dawei Lu, Oleg Shchekin
  • Patent number: 10553584
    Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Martin M. Frank, Renee T. Mo, Vijay Narayanan, John Rozen
  • Patent number: 10553511
    Abstract: Chip scale package such as a chip scale package having a chip integrated therein to provide an integrated chip scale package.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: February 4, 2020
    Assignee: CUBIC CORPORATION
    Inventor: J. Robert Reid
  • Patent number: 10535741
    Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has a N+ implant source region. In one embodiment, a JFET is provided with a drain metal deposited over a backside of an N substrate, an n-type drift layer epitaxial grown over a topside of the N substrate, a buried P-type block layer deposited over the n-type drift layer, an implanted N+ source region on side walls of the lateral channel layer, and an source metal attached to the top of the p-layer and attached to the implanted N+ source region at the side. In one embodiment, the JFET further comprises a gate layer, and wherein the gate layer is a dielectric gate structure that enables a fully enhanced channel. In another embodiment, the gate layer is a p-type GaN gate structure that enables a partially enhanced channel.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: January 14, 2020
    Inventor: Gangfeng Ye