Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

Abstract: The present disclosure provides a photo sensing device including a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, wherein the silicon layer includes a first doped region adjacent to a first side of the photosensitive member, wherein the first doped region has a first conductivity type, and a second doped region adjacent to a second side of the photosensitive member opposite to the first side, wherein the second doped region has a second conductivity type different from the first conductivity type, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member, and a portion of the composite layer proximal to the first doped region is doped with a dopant having the first conductivity type.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.

Abstract: An electronic module comprises a substrate including a first surface and a second surface on a side opposite to the first surface, the second surface including a first region and a second region surrounding the first region, an electronic device attached to the first surface, a component attached to the first region of the second surface, a lid member positioned to face the electronic device, and a frame member attached to the substrate to support the lid member. A first member and a second member having a higher thermal conductivity than the first member are disposed at least on the second surface. At least a part of the second member is positioned to face the second region. At least a part of the first member is positioned between the second member and the component.

Abstract: The invention relates to a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell. The object of the invention is to propose a method for improving the ohmic-contact behaviour between a contact grid and an emitter layer of a silicon solar cell, in which the effects on materials caused by irradiation of the sun-facing side are further minimized. In addition, the method should also be applicable to silicon solar cells in which the emitter layer has a high sheet resistance.

Abstract: A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a source feature and a drain feature, a channel structure disposed between the source feature and the drain feature, a semiconductor layer disposed over the channel structure and the drain feature, a dielectric layer disposed over the semiconductor layer, a backside source contact over the source feature and extending through the semiconductor layer and the dielectric layer, and a backside power rail disposed over the dielectric layer and in contact with the backside source contact.

Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, a first doped region having a first conductivity type at a first side of the photosensitive member, wherein the first doped region is in the silicon layer, and a second doped region having a second conductivity type different from the first conductivity type at a second side of the photosensitive member opposite to the first side, wherein the second doped region is in the silicon layer, and the first doped region is apart from the second doped region, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material.

Abstract: A photodetector is provided. The photodetector includes a bottom electrode region in a semiconductor layer, a light absorption material in the semiconductor layer, and a first buffer layer sandwiched between a bottom surface of the light absorption material and the semiconductor layer. The first buffer layer includes, from bottom to top, a first Si layer, a first SiGe layer, a second Si layer, and a second SiGe layer. A first atomic percentage of Ge in the first SiGe layer is less than a second atomic percentage of Ge in the second SiGe layer. The photodetector further includes a top electrode region over the light absorption material.

Abstract: Discloses is a method of manufacturing a solar cell with an increased power generation area to increase the area used for actual power generation without increasing the size of the solar cell.

Abstract: Short-wave infrared (SWIR) focal plane arrays (FPAs) comprising a Si layer through which light detectable by the FPA reaches photodiodes of the FPA, at least one germanium (Ge) layer including a plurality of distinct photosensitive areas including at least one photosensitive area in each of a plurality of photosensitive photosites, each of the distinct photosensitive areas comprising a plurality of proximate steep structures of Ge having height of at least 0.5 ?m and a height-to-width ratio of at least 2, and methods for forming same.

Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a through-substrate contact that extends between the first plurality of channel members and the second plurality of channel members, between the first gate structure and the second gate structure, and through the backside dielectric layer.

Abstract: An arrangement for an optoelectronic component includes a substrate and an optical semiconductor chip arranged on the substrate. The optical semiconductor chip has an optically active region, a first optically non-active region, and a second optically non-active region. A connection structure connects a chip-side electrical connection to the optically active region. An electrical connection connects the chip-side electrical connection to a second substrate-side electrical connection. A coating is provided in a layer stack in the optically active region, in the first optically non-active region, and in the second optically non-active region. The layer stack includes a first layer and a second layer arranged above the first layer. The chip-side electrical connection and the connection structure in the first optically non-active region and the protective layer in the second optically non-active region are each arranged between the first layer and the second layer.

Abstract: Provided is a solar cell and a method for manufacturing the same, the method includes: forming a doped layer on a surface of a semiconductor substrate, the doped layer having a first doping concentration of a doping element in the doped layer; depositing, on a surface of the doped layer, a doped amorphous silicon layer including the doping element; selectively removing at least one region of the doped amorphous silicon layer; performing annealing treatment, for the semiconductor substrate to form a lightly doped region having the first doping concentration and a heavily doped region having a second doping concentration in the doped layer, the second doping concentration is greater than the first doping concentration; and forming a solar cell by post-processing the annealed semiconductor substrate. The solar cell and the method for manufacturing the same simplify the manufacturing process and improve conversion efficiency of the solar cell.

Abstract: Structures for an avalanche photodetector and methods of forming a structure for an avalanche photodetector. The structure includes a first semiconductor layer having a first portion and a second portion, and a second semiconductor layer stacked in a vertical direction with the first semiconductor layer. The first portion of the first semiconductor layer defines a multiplication region of the avalanche photodetector, and the second semiconductor layer defines an absorption region of the avalanche photodetector. The structure further includes a charge sheet in the second portion of the first semiconductor layer. The charge sheet has a thickness that varies with position in a horizontal plane, and the charge sheet is positioned in the vertical direction between the second semiconductor layer and the first portion of the first semiconductor layer.