Abstract: In an electron emission element having an emitter section for emitting electrons, the emitter section includes, on a first conductive electrode, a structure in which at least a first semiconductor layer, a second semiconductor layer, an insulating layer and a second conductive electrode are deposited sequentially; and the first and second semiconductor layers include at least one of carbon, silicon and germanium as a main component, and the first semiconductor layer includes at least one type of atoms among carbon atom, oxygen atoms and nitrogen atoms which is different from the main component.

Abstract: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

Abstract: A plurality of unit areas having one to a plurality of MOSFETs for implementing specific logic circuits are placed in a first direction. A first interconnection extending in the first direction is formed over each unit area. A second interconnection extending in the first direction is formed along the plurality of unit areas and outside the unit areas. Wiring dedicated areas provided with a third interconnection extending in a second direction intersecting the first direction are respectively provided between the adjacent unit areas. A logic circuit formed in each unit area has both a first connection form connected to the first interconnection and a second connection form connected to the third interconnection via the second interconnection according to combinations with the wiring dedicated areas adjacent thereto as needed.

Abstract: A package for an integrated circuit device having an optical cell is disclosed. A method of making the package also is disclosed. The package includes a base of molded encapsulant material. A metal leadframe is embedded in the plastic base at the upper surface of the base. Encapsulant material covers the lower and side surfaces of the die pad and the leads of the leadframe, but does not cover the upper surfaces of the die pad and leads. The side surfaces of the die pad and leads have locking features for engaging the encapsulant material. An optical integrated circuit device is attached to the exposed surface of the die pad. An adhesive bead is applied around the optical device on the exposed upper surface of the leads. An optically clear cover is placed on and, in some embodiments, pressed into the still-viscous adhesive bead. When hardened, the bead supports the cover above the optical device.

Abstract: A method for fabricating an integrated circuit chip includes the steps of: (a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of the circuit board unit; (b) forming a die having an upper surface provided with a plurality of solder pads; (c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed; (d) wire-bonding the solder pads to the contact pads via conductive wires; (e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and (f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.

Abstract: A method of forming a rhodium-containing layer on a substrate, such as a semiconductor wafer, using complexes of the formula LyRhYz is provided. Also provided is a chemical vapor co-deposited platinum-rhodium alloy barriers and electrodes for cell dielectrics for integrated circuits, particularly for DRAM cell capacitors. The alloy barriers protect surrounding materials from oxidation during oxidative recrystallization steps and protect cell dielectrics from loss of oxygen during high temperature processing steps. Also provided are methods for CVD co-deposition of platinum-rhodium alloy diffusion barriers.

Abstract: A method for fabricating a bipolar transistor comprising the steps of implanting portions 320 of a semiconductor material structure with ions to render the portions semi-insulating; forming an emitter contact region 332 at an exposed surface of a base layer 308 in a non-implanted portion of the material structure; forming an epitaxial layer of semiconductor material 322 over the exposed surface in an implanted portion of the material structure; and forming a base contact 330 over said epitaxial layer. In accordance with one embodiment of the invention, the method includes the further step of forming a second epitaxial layer of semiconductor material 324 over the first epitaxial layer 322 and then forming the base contact 330 on the second epitaxial layer 324. In accordance with another embodiment, the method includes the farther step of forming a second layer of epitaxial material over the exposed surface prior to forming the epitaxial layer of semiconductor material.

Abstract: An active matrix type display device having a sufficient auxiliary capacitance and a high aperture ratio is provided. In the device, an auxiliary capacitance (a black mask being in contact with an inorganic layer/the inorganic layer/a pixel electrode being in contact with the inorganic layer) is formed on an interlayer insulating film made of an organic resin film.

Abstract: A non-volatile memory device and a fabrication method thereof, wherein the non-volatile memory device includes first and second memory cells in a region of a semiconductor substrate where a word line crosses a bit line. Thus, one word line can control the operation of two memory cells, and the device requires less area. Further an intergate dielectric layer extends to the side walls of the floating gate allowing more area and a higher coupling ratio. A lower voltage may therefore be applied to the control gate. During an erasing operation the path of electrons can be redirected toward the substrate. Deterioration of a tunneling insulating layer is thereby reduced or eliminated.

Abstract: Disclosed is a method for making an air bridge in an electronic device. This method uses amorphous silicon carbide to protect electrical conductors in the device during formation of the bridge. The silicon carbide also provides hermetic and physical protection to the device after formation.

Abstract: A package for integrated circuit chips. The package contains a silicon substrate having a top surface and a bottom surface. The package also contains a first means for electrically connecting the integrated circuits to the substrate attached to the top surface of the substrate. A multilevel wiring is located at the top surface and is coupled to the first connecting means and serves as a communication link among a plurality of the first connecting means to enable multi-chip processing. A via containing means for coupling the multilevel wiring at the top surface to the bottom surface runs through the substrate from the bottom surface to the top surface. A second means is also present for connecting the coupling means at the bottom surface of the substrate with external components.

Abstract: A semiconductor chip package having an internal laterally curved lead in order to compensate for the CTE mismatch between a semiconductor chip and a supporting substrate, such as a PWB.

Abstract: To increase the rate or speed of formation of a thermal oxide film of a silicon carbide semiconductor device, the partial pressure of water vapor is controlled to within the range of 0.1 to 0.95 when a surface of silicon carbide is oxidized under a mixed atmosphere of water vapor and oxygen. In a pyrogenic oxidation method in which hydrogen and oxygen are introduced to perform thermal oxidation, the ratio of the flow rate of hydrogen to that of oxygen is controlled to within the range of 1:0.55 to 1:9.5. In another pyrogenic oxidation method in which hydrogen and oxygen are introduced to perform thermal oxidation, a large portion of an oxide film is formed while the ratio of the flow rate of hydrogen to that of oxygen is controlled to about 1:4.5, and a remaining portion of the oxide film is then formed while the ratio of the flow rate of hydrogen to that of oxygen is controlled to about 1:0.55.

Abstract: A flip chip having solder bumps, an integrated underfill, and a separate flux coating, as well as methods for making such a device, is described. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes which heretofore have required a separate underfilling step.

Abstract: Methods for making an aluminum-containing metallization structure, methods and solutions for cleaning a polished aluminum-containing layer, and the structures formed by these methods. The methods for making the aluminum-containing metallization structure are practiced by providing a substrate, forming a metal layer with an upper surface containing aluminum over the substrate, polishing the metal layer, and contacting the polished surface of the metal layer with a solution comprising water and at least one corrosion-inhibiting agent. The method for cleaning the polished aluminum-containing layer is practiced by contacting a polished aluminum-containing layer with a solution comprising water and a corrosion-inhibiting agent. In these methods and solutions, the water may be deionized water, the corrosion-inhibiting agent may be citric acid or one of its salts, and the solution may contain additional additives, such as chelating agents, buffers, oxidants, anti-oxidants, and surfactants.

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract: A method of fabricating a flash memory integrated circuit is described. In an embodiment of the present invention a dielectric filled trench isolation region is formed in a silicon substrate. The dielectric filled trench isolation region isolates a first portion of the silicon substrate from a second portion of the silicon substrate. A portion of the dielectric in the trench is then removed to reveal a portion of the silicon substrate in the trench between the first and second portions of the silicon substrate. Ions are then implanted to form a first source region in the first portion of the silicon substrate and to form a second source region in the second portion of the silicon substrate and to form a doped region in the revealed silicon substrate in the trench wherein the doped region in the trench extends from the first doped source region to the second doped source region.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

Abstract: This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the gate having a polysilicon layer filling the trenches padded by a double gate-oxide structure. The double gate-oxide structure includes a thick-oxide-layer covering walls of the trench below an upper portion of the trench and a thin-gate-oxide covering walls of the upper portion of the trench thus defining a champagne-glass shaped gate in the trench. The DMOS power device further includes a source region of the first conductivity type disposed in the substrate surrounding a top portion of the trench. The DMOS power device further includes a body region of a second conductivity type disposed in the substrate surrounding the trench and encompassing the source region.