Abstract: A computer memory controller for interfacing to a host computer comprises a buffer memory for interfacing to a plurality of memory units and for holding data read thereto and therefrom. A central controller is operative to control the transfer of data to and from the host computer and the memory units. The buffer memory is controlled to form a plurality of buffer segments for addressably storing data read from or written to the memory units. The central controller is operative to allocate a buffer segment for a read or write request from the host computer, of a size sufficient for the data. The central controller is also operative in response to data requests from the host computer to control the memory units to seek a plurality of requested data stored in different memory units simultaneously.

Abstract: An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit.

Abstract: A software architecture and method for controlling multi-thread peripheral operations in an initiator device such as a computer equipped with a SCSI interface. A data structure is provided for storage of thread context parameters. High level code places a low level driver in either a single-thread or multi-thread mode, and then issues peripheral commands by calling the low level driver. The low level driver manages the interface protocol, returning to the high level code when a command is complete, or if in multi-thread mode, when a command disconnects. Management of the data structure is accomplished by the low level driver, minimizing the impact of multi-thread operations on the high level code.

Abstract: A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block in another processor's cache and the request is pending completion. All subsequent read requests for the data block during the pendency of the first request are inhibited until completion of the first request. Also provided in the memory directory for each data block is a field for identifying the processor which owns the data block in question. Data block ownership information is used to determine where requested owned data is located.

Abstract: A data processing unit according to the present invention has a central processing unit, and an analog-to-digital converter circuit associated with a plurality of input nodes respectively supplied with analog signals. The analog-to-digital converter circuit is established in one of three modes of operations, i.e., a fixed mode of operation for focusing the A/D converting operation on one analog signal of a specified input node, a scanning mode of operation for sequentially converting the analog signals into corresponding digital signals and a mixed mode of operation for performing the fixed mode of operation once or a predetermined number of times before automatically returning to the scanning mode of operation, so that the central processing unit does not need to shift the analog-to-digital converter circuit from the fixed mode to the scanning mode if the mixed mode is selected, thereby improving the throughput of the central processing unit.

Abstract: A method and system for sending data from a first computer through a communications line to a second computer. The second computer includes a redirector, a transport, a data buffer, and an application program. The method and system provides the transport with a read request to send data from the first computer to the second computer, and with a receive network control block which directs the transport to store the next data it receives directly in the data buffer. The transport sends the read request to the first computer. The first computer stores the data identified by the read request in a data block without a header. The first computer transmits the data block over the communications line to the transport. Using information contained in the network control block, the transport stores the requested data without the header directly in the data buffer.