Patents Examined by Edward Chin
  • Patent number: 10784276
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
  • Patent number: 10777775
    Abstract: A method for making a flexible display device includes: providing a hard substrate and sequentially forming a sacrificial layer, a metal layer, a buffer layer, and a flexible layer on the hard substrate; forming a display element layer on a surface of the flexible layer away from the buffer layer; hot pressing a laminate formed by the display element layer, the flexible layer, the buffer layer, the metal layer, the sacrificial layer, and the hard substrate to make the display element layer to bond to the flexible layer; laser irradiating the laminate from a side of the hard substrate to make the metal layer and the sacrificial layer peel off from each other.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: September 15, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Liang-Neng Chien, Yi-Hsiang Lin
  • Patent number: 10777545
    Abstract: A semiconductor device configures a protection element that protects a protection target element connected between a cathode electrode and an anode electrode when a parasitic transistor configured by a cathode region, a first conductivity type well layer, and a second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode. The semiconductor device includes a plurality of body regions in one cell of the protection element, and the plurality of body regions is brought in contact with the cathode electrode.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 15, 2020
    Assignee: DENSO CORPORATION
    Inventors: Akira Yamada, Shinya Sakurai, Takashi Nakano, Yosuke Kondo, Mutsuya Motojima
  • Patent number: 10777458
    Abstract: A method of filling a via hole and an apparatus for performing the same are disclosed. The method includes providing a filling material having a fluidity on a via hole formed in the substrate, forming an electric field through the substrate to fill the via hole with the filling material, and solidifying the filling material in the via hole. The apparatus includes a stage for supporting the substrate, upper and lower electrodes for forming the electric field, and a power supply connected with the upper and lower electrodes.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 15, 2020
    Assignee: SEMES CO., LTD.
    Inventors: Yoon Ki Sa, Mong Ryong Lee
  • Patent number: 10770536
    Abstract: A flexible display apparatus includes: a flexible substrate including a bending area and a non-bending area; and a wiring line extending across the bending area. The bending area is configured to bend along a bending axis, and a portion of the wiring line at the bending area includes a plurality of recessed portions recessed in a width direction of the wiring line.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Cheolkyu Kim, Gwangbum Ko, Sangkyu Choi, Sangyoun Han
  • Patent number: 10770513
    Abstract: A display device may include a first transistor, a first electrode, a second electrode, a first intermediate layer, and a first changeable layer. The first electrode is electrically connected to the first transistor. The second electrode overlaps the first electrode. The first intermediate layer is positioned between the first electrode and the second electrode and may emit first light when the first electrode and the second electrode generate a first electric field. The first changeable layer, which overlaps the first electrode, may have a first transmittance value when the first electrode and the second electrode generate the first electric field, and may have a second transmittance value when the first electrode and the second electrode do not generate the first electric field. The second transmittance value is unequal to the first transmittance value.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Yeon Chae, Sung-Young Choi
  • Patent number: 10762941
    Abstract: A spin-orbit torque magnetization rotating element includes a spin-orbit torque wiring and a laminated body laminated on the spin-orbit torque wiring. The laminated body includes a first ferromagnetic layer independently having an axis of easy magnetization in a first direction, a nonmagnetic antiferromagnetic coupling layer, and a second ferromagnetic layer independently having an axis of easy magnetization in a second direction, in order from the side of the spin-orbit torque wiring, and the first direction crosses the second direction.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: September 1, 2020
    Assignee: TDK CORPORATION
    Inventor: Yohei Shiokawa
  • Patent number: 10763212
    Abstract: A semiconductor structure includes a substrate including a surface, a first doped region and a second doped region, wherein the first doped region and the second doped region are disposed under the surface; a gate structure disposed between the first doped region and the second doped region; a capacitor disposed over and electrically connected to the first doped region; and a bit line disposed over and electrically connected to the second doped region, wherein the bit line includes a conductive portion and an insulating portion surrounding the conductive portion, and the insulating portion includes ferroelectric material.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Cheng-Hsien Hsieh, Ching-Chia Huang, Chen-Lun Ting, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10755921
    Abstract: A method of manufacturing a semiconductor device, includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing (a) supplying a precursor containing a first element to the substrate, (b) supplying a plasma-excited nitrogen gas to the substrate after the act (a), (c) supplying a reactant containing a second element to the substrate after the act (b), and (d) supplying a plasma-excited nitrogen gas to the substrate after the act (c). A gas purge of a space where the substrate is located and vacuumization of the space without gas supply are not performed between the act (a) and the act (b) and between the act (c) and the act (d).
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 25, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Tatsuru Matsuoka
  • Patent number: 10727131
    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Mu Li, Chih-Chiang Chang, Wen-Chu Hsiao, Che-Yu Lin, Wei-Siang Yang
  • Patent number: 10727335
    Abstract: A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: July 28, 2020
    Assignee: Sony Corporation
    Inventor: Koichi Amari
  • Patent number: 10710872
    Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
  • Patent number: 10714476
    Abstract: A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmin Kim, Dongwon Kim
  • Patent number: 10699884
    Abstract: According to one embodiment, a plasma processing apparatus includes a processing chamber, a sample stage that is disposed inside the processing chamber and electrically divided into a plurality of regions on which a sample is placed, an electromagnetic wave introduction unit that introduces electromagnetic waves into the processing chamber, and a bias power applying unit that applies bias power to the sample stage, in which the bias power applying unit is configured to include a first radio frequency power applying unit that applies first radio frequency power to a first region out of the plurality of electrically divided regions of the sample stage, a second radio frequency power applying unit that applies second radio frequency power to a second region out of the plurality of electrically divided regions of the sample stage, and a phase adjuster that controls the first radio frequency power applying unit and the second radio frequency power applying unit to shift the phases of the first radio frequency powe
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: June 30, 2020
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Kazuya Yamada, Koichi Yamamoto, Naoki Yasui, Norihiko Ikeda, Isao Mori
  • Patent number: 10700016
    Abstract: A protective film material for laser processing comprises a solution of a water-soluble adhesive and a water-soluble laser beam absorbent added to adjust absorbance at a wavelength of 355 nm (absorbance as calculated as a 200-times diluted solution) to 0.3 to 3. The protective film effectively absorbs an irradiated laser beam, reduces generation of debris during laser beam irradiation, and can be removed by washing with water after completion of the laser processing treatment, thereby providing reliable processing. The water-soluble adhesive is preferably a blend of polyvinyl alcohol and poly-N-vinyl acetamide, which are preferably blended at a ratio of 100 to 200:1 in terms of amounts of respective components.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: NIKKA SEIKO CO., LTD.
    Inventors: Tsuyoshi Tadano, Masafumi Hirose, Daisuke Tomita
  • Patent number: 10689247
    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 10692843
    Abstract: A flexible polymeric dielectric layer (12) having first and second major surfaces, the first major surface having a conductive layer (20) thereon, the dielectric layer having at least one conduit (10) extending from the second major surface to the first major surface, the conduit having at least one lateral dimension of at least about one centimeter and being at least partially filled with conductive material (18), the conductive layer including at least one conductive feature (21) substantially aligned with the conduit (10), the conductive feature (21) supporting a plurality of light emitting semiconductor devices (22).
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 23, 2020
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ravi Palaniswamy, Jian Xia Gao, Alejandro Aldrin A. Narag, II, Nathan P. Kreutter, Andrew J. Ouderkirk
  • Patent number: 10693000
    Abstract: A semiconductor device includes a plurality of first field-effect structures each including a polysilicon gate arranged on and in contact with a first gate dielectric, and a plurality of second field-effect structures each including a metal gate arranged on and in contact with a second gate dielectric. The plurality of first field-effect structures and the plurality of second field-effect structures form part of a power semiconductor device.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies Austria AG
    Inventor: Walter Rieger
  • Patent number: 10692766
    Abstract: A method of cutting a workpiece includes forming a guide groove to a depth smaller than the predetermined depth in the workpiece, the guide groove extending from the outer peripheral edge to an end portion of the device area, by causing a cutting blade to cut into the workpiece held on the holding surface of the chuck table from an outer peripheral edge of the workpiece along one of the projected dicing lines; and forming a groove to the predetermined depth in the workpiece along the projected dicing line, the groove extending from the device area beyond an opposite end of the device area to a portion of the outer peripheral extra area, after lowering the cutting blade toward and into the guide groove in the device area and then positioning a cutting edge thereof at the predetermined depth.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: June 23, 2020
    Assignee: DISCO CORPORATION
    Inventors: Makoto Tanaka, Takatoshi Kyo, Chan Kit Chee
  • Patent number: 10685969
    Abstract: A read-only memory (ROM) structure is provided. The ROM device structure includes a first gate structure formed over a substrate, and the first gate structure includes a first work function layer with a first thickness. The ROM device structure includes an isolation structure formed over the substrate, and the isolation structure is adjacent to the first gate structure. The isolation structure includes a second work function layer with a second thickness, and the second thickness is larger than or smaller than the first thickness. The ROM device structure also includes a first contact structure formed over the substrate, and the first contact structure is between the first gate structure and the isolation structure.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Hung Hsieh