Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

Abstract: A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region therebetween, a cell device isolation pattern on the cell region of the substrate to define cell active patterns, a peripheral device isolation pattern on the peripheral region of the substrate to define peripheral active patterns, and an insulating isolation pattern on the boundary region of the substrate, the insulating isolation pattern being between the cell active patterns and the peripheral active patterns, wherein a bottom surface of the insulating isolation pattern includes a first edge adjacent to a side surface of a corresponding one of the cell active patterns, and a second edge adjacent to a side surface of a corresponding one of the peripheral active patterns, the first edge being at a height lower than the second edge, when measured from a bottom surface of the substrate.

Abstract: A memory device includes a substrate, a conductive line, a capacitor, a transistor, and a contact structure. The conductive line is above a peripheral region of the substrate. The capacitor is above a memory region of the substrate. The transistor is above and connected to the capacitor and includes first and second source/drain regions, a channel, and a gate structure. The first source/drain region is connected to the capacitor. The gate structure laterally surrounds the channel. The contact structure is above the peripheral region and includes a bottom portion, a top portion, and a middle portion. The bottom portion is connected to the conductive line. The top portion is connected to the second source/drain region. The middle portion is wider than the top portion and the bottom portion, in which the middle portion of the contact structure is at a height substantially level with the gate structure.

Abstract: A micro semiconductor device and a micro semiconductor display are provided. The micro semiconductor device includes an epitaxial structure, a first electrode, a second electrode and a supporting layer. The epitaxial structure has a bottom surface and a top surface, wherein the bottom surface is defined as a central region and a peripheral region. A first electrode and a second electrode are disposed on the central region of the bottom surface of the epitaxial structure, or the first electrode is disposed on the central region of the bottom surface of the epitaxial structure and the second electrode is disposed on the top surface of the epitaxial structure. The supporting layer is disposed on the peripheral region of the bottom surface of the epitaxial structure.

Abstract: A method for fabricating a semiconductor device includes: forming a mold stack layer including a mold layer and a supporter layer over a substrate; forming opening by etching the mold stack layer; selectively forming a supporter reinforcement layer on an exposed surface of the supporter layer which is positioned in the opening; forming a bottom electrode in the opening in which the supporter reinforcement layer is formed; and forming a supporter opening by etching a portion of the supporter layer to form a supporter that supports an outer wall of the bottom electrode.

Abstract: Systems and methods for controlling contamination during thermocompression bonding are provided herein. The tool generally includes a bondhead having a first channel extending in a lateral direction from a first port along a second side toward a perimeter of the bondhead. In several examples, the bondhead includes a second channel fluidly coupled to a second port and extending in a lateral direction along an inset surface of the bondhead, where the second channel at least partially surrounds the first channel. In other examples, the tool includes a vacuum manifold having a vacuum opening positioned laterally outward from the bondhead. A first flow unit is coupled to the first channel and is configured to withdraw air. A second flow unit is coupled to the second port or the manifold to withdraw fluid and prevent outgas sing bonding materials from entering the first channel, depositing on the bondhead, and/or contaminating neighboring semiconductor components.

Abstract: A semiconductor device includes a substrate including first and second region, a bit line structure on the first region, key structures on the second region, each key structure having an upper surface substantially coplanar with an upper surface of the bit line structure, a first trench disposed between two adjacent key structures spaced apart from each other in a first direction, a filling pattern in a lower portion of the first trench, the filling pattern having a flat upper surface and including a first conductive material, and a first conductive structure on the flat upper surface of the filling pattern, an upper sidewall of the first trench, and the upper surface of each of the plurality of key structures, the first conductive structure including a second conductive material.

Abstract: A sensor package includes a sensor, at least one external wall, and an interposer, arranged between the sensor and the at least one external wall. The sensor is wire bonded to the interposer and the interposer is wire bonded to the at least one external wall. Using an interposer, wire bonded to both the sensor and the at least one external wall, is an improved approach to electrically connecting a sensor and a sensor package. The interposer allows for short wire bonds from the sensor and the at least one external wall to the interposer, replacing the single, long wire bond from the sensor to the at least one external wall in the prior art. This provides improved resilience of the sensor package under high stress. Furthermore, it allows an existing sensor and package combination to be improved without needing to redesign either component.

Abstract: A layout structure of a capacitance cell using vertical nanowire (VNW) FETs is provided. The capacitance cell includes a plurality of first-conductivity type VNW FETs lining up in the X direction, provided between a first power supply interconnect and a second power supply interconnect. The plurality of first-conductivity type VNW FETs include at least one first VNW FET having a top and a bottom connected with the first power supply interconnect and a gate connected with the second power supply interconnect.

Abstract: A thin film transistor includes a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are on the substrate. The active layer includes a channel region between the source electrode and the drain electrode and the channel region includes an edge region along a channel length direction and a main region outside the edge region. The thin film transistor further includes an auxiliary layer, a projection of the auxiliary layer on the substrate is at least partially overlapped with a projection of the edge region of the channel region on the substrate, and the auxiliary layer is configured to enhance a turn-on voltage of the edge region of the channel region.

Abstract: Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

Abstract: Systems and methods discussed herein can be used to form gratings at various slant angles across a grating material on a single substrate by determining an ion beam angle and changing the angle of an ion beam among and between ion beam angles to form gratings with varying angles and cross-sectional geometries. The substrate can be rotated around a central axis, and one or more process parameters, such as a duty cycle of the ion beam, can be modulated to form a grating with a depth gradient.

Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate; forming at least one sacrificial layer and at least one liner layer, that are alternately stacked over each other, on the substrate; etching the at least one liner layer and the at least one sacrificial layer until the substrate is exposed, to form a plurality of fins, discretely arranged on the substrate; and etching a portion of a thickness of the substrate, such that a width of the etched portion of the substrate at a bottom of the at least one sacrificial layer is less than a width of the at least one liner layer of the plurality of fins.

Abstract: Disclosed are semiconductor devices including support patterns and methods of fabricating the same. The semiconductor devices may include a plurality of vertical structures on a substrate and a support pattern that contacts sidewalls of the plurality of vertical structures. The support pattern may include a plurality of support holes extending through the support pattern. The plurality of support holes may include a first support hole and a second support hole that are spaced apart from each other, and the first support hole may have a shape or size different from a shape or size of the second support hole.

Abstract: Systems, methods and apparatus are provided for a three-node access device in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines. The method includes depositing alternating layers of a dielectric material and a sacrificial material to form a vertical stack. Forming a plurality of first vertical openings to form elongated vertical, pillar columns with sidewalls in the vertical stack. Conformally depositing a gate dielectric in the plurality of first vertical openings. Forming a conductive material on the gate dielectric. Removing portions of the conductive material to form a plurality of separate, vertical access lines. Repairing a first side of the gate dielectric exposed where the conductive material was removed. Forming a second vertical opening to expose sidewalls adjacent a first region of the sacrificial material.

Abstract: A memory device includes a substrate, an active layer that is spaced apart from the substrate and laterally oriented, a word line that is laterally oriented in parallel to the active layer along one side of the active layer, an active body that is vertically oriented by penetrating through the active layer, a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body, and a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.

Abstract: A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer.

Abstract: A field effect transistor, a method of manufacturing the field effect transistor, and an electronic device are provided, wherein the field effect transistor comprises: a source(105) formed of a Dirac material(103) and a drain(107); a channel(102) disposed between the source(105) and the drain(107); and a source control electrode(108) disposed on the source(105) and for controlling the doping of the Dirac material(103) such that the Dirac material(103) and the channel(102) are doped in an opposite manner; and a gate(106) disposed on the channel(102) and electrically insulated from the channel(102).

Abstract: A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate and including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A first at least one non-semiconductor monolayer may be constrained within the crystal lattice of a first pair of adjacent base semiconductor portions and comprise a first non-semiconductor material, and a second at least one non-semiconductor monolayer may be constrained within the crystal lattice of a second pair of adjacent base semiconductor portions and comprise a second non-semiconductor material different than the first non-semiconductor material.

Abstract: A method for distributing deep trench (DT) capacitance in an integrated circuit (IC) design is provided. The method includes forming a placement block that includes blockages defining openings in interstitial regions among the blockages, superimposing the placement block over the IC design and providing distributed DT capacitance to the IC design. The providing of the distributed DT capacitance includes adding DT capacitance cells through the openings to portions of the IC design where there are no reserved blocks.