Patents Examined by Elias Mamo
  • Patent number: 11182096
    Abstract: A fault-tolerant data storage system associates durability requirements of service level agreements (SLAs) for volumes stored in the fault-tolerant data storage system with volume partitions stored in the fault-tolerant data storage system. For a given volume partition, volume data is stored in two or more replicas on two or more different system components and/or erasure encoded across multiple other system components. The fault-tolerant data storage system uses the respective durability requirements of the SLAs and failure statistics of the system components to allocate bandwidth for replacing lost instances of redundantly stored volume data such that the lost data is replaced within a target time calculated to guarantee the durability requirements of the SLAs are satisfied.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 23, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Kun Tang, Hon Ping Shea
  • Patent number: 11182856
    Abstract: Systems and methods are disclosed for routing of streaming data as between multiple compute resources. For example, the system may comprise a processor, a field programmable gate array (FPGA), a shared memory that is shared by a user space of an operating system for the processor and the FPGA, a network protocol stack, and driver code for execution by the processor. The driver code can be configured to (1) make the received streaming data available to a user mode software application for processing, (2) make data stored in the shared memory available to the FPGA via DMA transfers of data from the shared memory into the FPGA for processing thereby, (3) receive a stream of processed data from the FPGA, and (4) provide the received processed data to the network protocol stack for delivery to one or more data consumers.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: November 23, 2021
    Assignee: Exegy Incorporated
    Inventors: Scott Parsons, David E. Taylor, David Vincent Schuehler, Mark A. Franklin, Roger D. Chamberlain
  • Patent number: 11176032
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 16, 2021
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11176064
    Abstract: Methods and apparatus for reducing bus overhead with virtualized transfer rings. The Inter-Processor Communications (IPC) bus uses a ring buffer (e.g., a so-called Transfer Ring (TR)) to provide Direct Memory Access (DMA)-like memory access between processors. However, performing small transactions within the TR inefficiently uses bus overhead. A Virtualized Transfer Ring (VTR) is a null data structure that doesn't require any backing memory allocation. A processor servicing a VTR data transfer includes the data payload as part of an optional header/footer data structure within a completion ring (CR).
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Apple Inc.
    Inventors: Karan Sanghi, Saurabh Garg, Vladislav V. Petkov
  • Patent number: 11175840
    Abstract: An apparatus in one embodiment comprises a host device comprising a processor coupled to memory. The host device is configured to communicate over a network with at least one storage system. The host device is further configured to generate a user space block device and to generate a kernel space block device corresponding to the user space block device. The host device is further configured to receive an input-output operation at the kernel space block device from an application executing on the host device and to transfer the input-output operation from the kernel space block device to the corresponding user space block device. The host device is further configured to submit the input-output operation to the at least one storage system based at least in part on the user space block device.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Md Haris Iqbal, Kundan Kumar
  • Patent number: 11157181
    Abstract: A card activation device includes a first control unit and a central control unit. In response to a first control command, the central control unit provides first authentication data to the first control unit and the first control unit transmits the first authentication data to the data storage device. After the first authentication data is transmitted to the data storage device, the central control unit provides second authentication data to the first control unit and the first control unit transmits the second authentication data to the data storage device. After the second authentication data is transmitted to the data storage device, the card activation device enters a fully locked state and performs an authentication procedure for authenticating the data storage device. Before the data storage device has passed the authentication procedure, the central control unit is not allowed to transmit any data to the data storage device.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 26, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Te-Kai Wang, Hsing-Lang Huang
  • Patent number: 11144245
    Abstract: A memory control method is disclosed. The method includes: determining a mode for reading first data in a first management unit as a first mode or a second mode according to a data dispersion degree of the first data; reading the first data from the first management unit according to a physical distribution of the first data if the mode for reading the first data is determined as the first mode; and reading the first data from the first management unit according to a logical distribution of the first data if the mode for reading the first data is determined as the second mode. Furthermore, a memory storage device and a memory control circuit unit are also disclosed.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 12, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Che-Yueh Kuo
  • Patent number: 11144465
    Abstract: In a data access method, after an interface card receives a first data write instruction or a first data read instruction, the interface card generates a second data write instruction or a second data read instruction, and writes the second data write instruction or the second data read instruction into a cache. No resource of a processor of a storage device is used. After the interface card writes the second data write instruction or the second data read instruction into the cache, a cache control unit sends the second data write instruction or the second data read instruction to a storage subsystem. No resource of the processor of the storage device is used. Alternatively, the cache control unit may instruct the storage subsystem to execute the second data write instruction or the second data read instruction.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 12, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jian He, Xiaoke Ni
  • Patent number: 11144485
    Abstract: An interface for a semiconductor device includes a master device and a plurality of slave devices. The interface includes a master interface and a slave interface. The master interface is implemented in the master device and includes a master bond pattern of master bonds arranged as a first array. The slave interface is implemented each slave device and includes a slave bond pattern of slave bonds arranged as a second array. The first array of the master bonds includes a first central row and first data rows in two parts being symmetric to the first central row. The second array of the slave bonds includes a second central row and second data rows in two parts being symmetric to the second central row. The first central row and the second central row are aligned in connection, and the first data rows are connected to the second data rows.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 12, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Igor Elkanovich, Amnon Parnass, Pei Yu, Li-Ken Yeh, Yung-Sheng Fang, Sheng-Wei Lin, Tze-Chiang Huang, King Ho Tam, Ching-Fang Chen
  • Patent number: 11144085
    Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Asma H. Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Dorit Shapira, Krishnakanth Sistla, Nikhil Gupta, Vasudevan Srinivasan, Chris MacNamara
  • Patent number: 11138102
    Abstract: A method and apparatus to reduce read latency and improve read quality of service (Read QoS) for non-volatile memory, such as NAND array in a NAND device. For read commands that collide with an in-progress program array operation targeting the same program locations in a NAND array, the in-progress program is suspended and the controller allows the read command to read from the internal NAND buffer instead of waiting for the in-progress program to complete. For read commands queued during an in-progress program that is processing pre-reads in preparation for a program array operation, pre-read bypass allows the reads to be serviced between the pre-reads and before the program's array operation starts. In this manner, read commands can be serviced without suspending the in-progress program. Allowing internal NAND buffer reads and enabling pre-read bypass reduces read latency and improves Read QoS.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Sagar S. Sidhpura, Yogesh B. Wakchaure, Aliasgar S. Madraswala, Fei Xue
  • Patent number: 11132140
    Abstract: Method and apparatus for enhancing performance of a storage device, such as a solid-state drive (SSD). A non-volatile memory (NVM) stores user data from a client device. Map metadata in a local memory describes locations of the user data in the NVM. The map metadata is arranged as a snapshot and accumulated journal updates. A metadata manager circuit combines a first portion of the journal updates with the existing snapshot to generate a new snapshot, and places a second portion of the journal updates into a read-only journal table in accordance with a selected metadata journaling strategy. A controller uses the updated snapshot and the table to service subsequently received client commands. Only dirty entries are processed and are written at the slowest acceptable rate, thereby improving client I/O performance during normal operation and time to ready (TTR) performance of the device during initialization.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 28, 2021
    Assignee: Seagate Technology, LLC
    Inventors: Daniel John Benjamin, Ryan James Goss
  • Patent number: 11126382
    Abstract: It discloses a technical solution of the present disclosure partitions a high-speed data code stream into a plurality of sequentially arranged data blocks so as to write the data blocks sequentially to a circular cache. The circular cache is comprised of N cache segments that share a write pointer, each cache segment owning an independent read pointer. The data blocks are sequentially written into the N cache segments; data will be continuously written to the 1st cache segment; data will be read from the cache segment at a relatively low rate and written to a corresponding SD card, thereby implementing data speed reduction; a controller will integrate the disordered data into a same SD card following the original arrangement order, thereby completing all data storage work.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 21, 2021
    Assignee: SHANDONG UNIVERSITY
    Inventors: Yong Wang, Zhe Wang, Hongyu Li, Feng Zhou
  • Patent number: 11126574
    Abstract: A data processing system comprises compile time logic, runtime logic, a control bus, and instrumentation units operatively coupled to processing units of an array. The compile time logic is configured to generate configuration files for a dataflow graph. The runtime logic is configured to execute the configuration files on the array, and to trigger start and stop events, as defined by the configuration files, in response to implementation of compute and memory operations of the dataflow graph on the array. A control bus is configured to form event routes in the array. The instrumentation units have inputs and outputs connected to the control bus and to the processing units. The instrumentation units are configured to consume the start events on the inputs and start counting clock cycles, consume the stop events on the inputs and stop counting the clock cycles, and report the counted clock cycles on the outputs.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: September 21, 2021
    Assignee: SambaNova Systems, Inc.
    Inventors: Raghu Prabhakar, Matthew Thomas Grimm, Sumti Jairath, Kin Hing Leung, Sitanshu Gupta, Yuan Lin, Luca Boasso
  • Patent number: 11119947
    Abstract: A method for secure hardware initialization during a start-up process comprises activating a protected portion of a physical memory, allocating a part of the protected portion of the physical memory for use by direct memory access, DMA, drivers and non-DMA related hardware initialization instructions, and using a memory management tool, allocating a first part of the physical memory, accessible by a device via the memory management tool, for use by data.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: September 14, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Maugan Villatel, Chris Dalton, Carey Huscroft
  • Patent number: 11106390
    Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a first read command from a command queue is forwarded to a non-volatile memory (NVM) to request retrieval of a first set of readback data. While the NVM initiates in-process execution of the first read command, an expanded read command is issued to the NVM. The expanded read command supercedes the first read command and requests an expanded set of readback data that includes the first set of readback data as well as a second set of readback data. The second set of readback data may be associated with a second read command in the command queue. The NVM transfers the expanded set of readback data to a read buffer responsive to the expanded read command. The first and second read commands may be client reads, background reads or both.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 31, 2021
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Daniel John Benjamin, David W. Claude, Graham David Ferris, Ryan Charles Weidemann
  • Patent number: 11106612
    Abstract: Embodiments relate to coordinating the operations of subsystems in a communication system of an electronic device where a coexistence hub device monitors the state information transmitted as coexistence messages over one or more multi-drop buses, processes the monitored coexistence messages and sends out control messages as coexistence messages to other systems on chips (SOCs). The coexistence hub device can also update the operations of the communication system. The coexistence hub device may receive an operation policy from a central processor and may execute the operation policy without further coordination of the central processor. The coexistence hub device broadcasts the control messages as coexistence messages according to the executed operation policy.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: August 31, 2021
    Assignee: APPLE INC.
    Inventors: Helena Deirdre O'Shea, Matthias Sauer, Jorge L. Rivera Espinoza, Bernd Adler
  • Patent number: 11086778
    Abstract: Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 10, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Chirca, Timothy David Anderson, Joseph Zbiciak, David E. Smith, Matthew David Pierson
  • Patent number: 11086563
    Abstract: A storage device includes a memory controller to receive a first signal from an external device through a first channel, obtain data from a memory based on the first signal, and output the data to the external device through a second channel. The data is output through the second channel in a case where a time interval between a time when the first signal is received and a time when the data are obtained is greater than a first reference interval.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonbong Kim, Mina Hwang, Hojun Shim, Kwanggu Lee
  • Patent number: 11086557
    Abstract: A system identifies (I) a first independent filesystem that (i) includes a file and (ii) uses file-handles to locate files and (II) a second independent filesystem that (i) operates independently of file-handles, associated with the first independent filesystem, when locating files and (ii) includes a copy of the file. The system generates a file-handle for the copy of the file on an inode of first independent filesystem based on a full-path for the copy of the file on the second independent filesystem. The system replicates one or more data blocks between the first independent filesystem and the second independent filesystem based, at least in part, on the full-path.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Venkateswara Rao Puvvada, Karrthik K G, Ashish Pandey, Saket Kumar