Abstract: Methods and systems for managing queues. The disclosed methods involve receiving, at an interface, a request to store a message in a queue, storing the message as a row in a key-value store database, extracting at least one attribute from the message; and selecting the message for processing based on the at least one extracted attribute.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: Delaying deletion of a dataset, including: associating an eradication timer with the dataset, wherein the eradication timer specifies an amount of time to delay a requested deletion of the dataset; determining that the amount of time to delay the requested deletion of the dataset should be modified; and modifying the eradication timer to specify a modified amount of time to delay the requested deletion of the dataset.

Abstract: A data storage method for speech-related deep neural network (DNN) operations, characterized by comprising the following steps: 1. determining the configuration parameters by a user; 2. configuring a peripheral storage access interface; 3. configuring a multi-transmitting interface of feature storage array; 4. enabling CPU to store to-be-calculated data in a storage space between the feature storage space start address and the feature storage space end address of the peripheral storage device; 5. after data storage, enabling CPU to check the state of the peripheral storage access interface and the multi-transmitting interface of feature storage array; 6. upon receiving a transportation completion signal of the peripheral storage access interface by CPU, enabling the multi-transmitting interface of feature storage array. 7. upon receiving a transportation completion signal of the multi-transmitting interface of feature storage array by CPU, repeating step 6.

Abstract: An I/O server service interacts with multiple containerized controller services each implementing the same control routine to control the same portion of the same plant. The I/O server service may provide the same controller inputs to each of the containerized controller services (e.g., representing measurements obtained by field devices and transmitted by the field devices to the I/O server service). Each containerized controller service executes the same control routine to generate a set of controller outputs. The I/O server service receives each set of controller outputs and forwards an “active” set to the appropriate field devices. The I/O server service and other services, such as an orchestrator service, may continuously evaluate performance and resource utilization in the control system, and may dynamically activate and deactivate controller services as appropriate.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. In response to receiving a first write command from a host, the controller determines a first physical address indicative of a physical storage location of the nonvolatile memory to which first write data associated with the first write command is to be written, and updates an address translation table such that the first physical address is associated with a logical address of the first write data. The controller starts updating the address translation table before the transfer of the first write data is finished or before the write of the first write data to the nonvolatile memory is finished.

Abstract: A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

Abstract: The present application discloses self-learning file transmitting, data reading and writing, and APP communication reading and writing methods of a game handle. The self-learning file transmitting method includes the following steps: S1: initializing a chip and scanning a key value; S2: erasing a FLASH chip and forming a reminder of usage; S3: scanning the key value and starting timing; and S4: timing and scanning the key value, and forming a reminder showing the end of learning. The present application provides a learning AI key with a special function on the game handle, and the AI key function can record operations of all users and save them as data for internal storage.

Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

Abstract: A signal processing system is described. The signal processing system includes at least one signal processing path and a control module. The at least one signal processing path includes at least one signal input and at least two filter units. The at least two filter units include at least one hardware filter unit. The at least one signal input is connectable to at least one external electronic component. The control module is connected to the signal input and to the at least two hardware filter units. The control module is configured to determine a frequency response deviation being associated with the at least one external electronic component. The control module further is configured to reconfigure the at least one hardware filter unit such that the frequency response deviation is compensated at least partially. Further, a signal processing method for adapting filter coefficients of a signal processing system is described.

Abstract: A computer implemented system and method of memory management for an in-memory database. The system implements a paged data vector using non-uniform compression of its chunks. In this manner, the system achieves greater compression than systems that use uniform compression.

Abstract: A processing device is provided which includes memory configured to store data and a processor configured to determine, based on convolutional parameters associated with an image, a virtual general matrix-matrix multiplication (GEMM) space of a virtual GEMM space output matrix and generate, in the virtual GEMM space output matrix, a convolution result by matrix multiplying the data corresponding to a virtual GEMM space input matrix with the data corresponding to a virtual GEMM space filter matrix. The processing device also includes convolutional mapping hardware configured to map, based on the convolutional parameters, positions of the virtual GEMM space input matrix to positions of an image space of the image.

Abstract: A calculation system includes a variable memory storing a value indicating a state of a variable of a mixed integer quadratic programming problem; a state transition calculation block that calculates the next state of the value indicating the state of the variable; a nonlinear coefficient memory that stores a nonlinear coefficient of the state transition calculation block; a linear coefficient memory that stores a linear coefficient of the state transition calculation block; a weight input line that receives a weight signal of the state transition calculation block; and a temperature input line that receives a temperature signal of the state transition calculation block. The state transition calculation block includes a difference calculation block that calculates a difference calculation by using the weight signal, the nonlinear coefficient, and the linear coefficient. A next state determination block calculates the next state of the variable using the value read from the variable memory.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: Configuration devices in a module. In some embodiments, a radio frequency module includes a serial bus including a first serial data line and a second serial data line. The radio-frequency module also includes a first switch coupled to a first device and a third line. The radio-frequency module further includes a module coupled to the serial bus and the first switch, the module configured to determine whether first data is detected on a first serial data line, determine whether second data is detected on a second serial data line, adjust a configuration of the first switch when the first data is detected on the first serial data line and the second data is detected on the second serial data line.

Abstract: A mode register data processing module is configured to write, in response to a mode register write enable command, first preset data into a reserved mode register in a mode register; an external data transmission module is configured to write, in response to an enable signal, initial data into a memory array via an internal data transmission module according to the first preset data and a preset encoding rule, and is further configured to read target data from the memory array in response to a read command; and a comparison module is configured to determine whether there is an abnormal data transmission based on a comparison result of the first preset data and the target data, and store the comparison result to a preset position in the mode register.

Abstract: An apparatus and method are provided for managing prefetch transactions. The apparatus has an interconnect for providing communication paths between elements coupled to the interconnect. The elements coupled to the interconnect comprise at least a requester element to initiate transactions, and a plurality of completer elements each of which is arranged to respond to a transaction received by that completer element. Congestion tracking circuitry maintains, in association with the requester element, a congestion indication for each of a plurality of routes through the interconnect used to propagate transactions initiated by that requester element. Each route comprises one or more communication paths, and the route employed to propagate a given transaction is dependent on a target completer element for that transaction.

Abstract: To improve utilization of a systolic array, each row of the array is provided with a number of general purpose row input data buses. Each of the general purpose row input data buses can be operable to transfer either feature map (FMAP) input elements or weight values into the processing elements of the corresponding row of the array. By using such general purpose row input data buses, concurrent matrix multiplications as well as faster background weight loading can be achieved in the array.

Abstract: Systems, apparatuses, and methods related to an isolation circuit in a memory module are described. A dual-in line memory module (DIMM), for example, may include an isolation circuit to isolate components from one another in certain operating modes or phases of module operation. The isolation circuit may, for instance, isolate one integrated circuit (e.g., an electrically erasable read-only memory (EEPROM)) that includes serial presence detect (SPD) information from a controller (e.g., a field programmable gate array (FPGA)) if the controller is not energized. The isolation circuit may be employed in a non-volatile DIMM (NVDIMM), and an integrated circuit of the NVDIMM (e.g., an SPD EEPROM) may be isolated from an FPGA of the NVDIMM while the NVDIMM is de-energized. The isolation circuit may be employed in other examples to isolate or couple, or both, different components from or to one another.

Abstract: An information handling system may include a processor, a device communicatively coupled to a processor via a communications link including a cable assembly, and a management controller communicatively coupled to the processor and communicatively coupled to the device and the cable assembly via a sideband interface, and configured to: retrieve, via the sideband interface, self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the device; retrieve, via the sideband interface, self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the cable assembly; combine the self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the device and the self-describing signal integrity critical parameters from non-transitory computer-readable media integral to the cable assembly into aggregate signal integrity critical parameters; and perform an action relevant to the co