Patents Examined by Eliseo Ramos-Feliciano
  • Patent number: 9929295
    Abstract: In various embodiments, photovoltaic modules are hermetically sealed by providing a first glass sheet, a photovoltaic device disposed on the first glass sheet, and a second glass sheet, a gap being defined between the first and second glass sheets, disposing a glass powder within the gap, and heating the powder to seal the glass sheets.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 27, 2018
    Assignee: SIVA POWER, INC.
    Inventor: Markus Eberhard Beck
  • Patent number: 9893315
    Abstract: A display device includes a display device including a substrate, and a display unit disposed on the substrate. An encapsulating unit encapsulates the display unit. The encapsulating unit includes a barrier organic layer. The barrier organic layer includes a plurality of organic materials and a plurality of inorganic materials. The inorganic materials are arranged in free volumes between the organic materials.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 13, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Seungyong Song, Hyojeong Kwon, Seunghun Kim, Myungmo Sung, Kwanhyuck Yoon
  • Patent number: 9887080
    Abstract: A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang-hun Moon, Yong-suk Tak, Gi-gwan Park
  • Patent number: 9875925
    Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-ho Kong, Jeong-hee Park, Taek-jung Kim, Han-young Kim, Keon-seok Seo, Jong-myeong Lee, Hee-sook Park
  • Patent number: 9870950
    Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Sun Hwang, Ja-Eung Koo, Jong-Hyung Park, Ho-Young Kim, Leian Bartolome, Bo-Un Yoon, Hyoung-Bin Moon
  • Patent number: 9870940
    Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark Rodder, Borna Obradovic
  • Patent number: 9842748
    Abstract: Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 12, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mehmet Tugrul Samir, Shu-Kwan Lau
  • Patent number: 9837629
    Abstract: An organic light emitting diode display including a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate and separated from the first electrode, a pixel defining layer disposed on the first electrode and the second electrode, a first organic emission layer disposed on the first electrode corresponding to the first opening, a second organic emission layer disposed on the second electrode corresponding to the second opening, and a common electrode disposed on the first organic emission layer and the second organic emission layer. The first electrode includes a first dent portion. The second electrode includes a second dent portion having a different size from the first dent portion. The pixel defining layer includes a first opening exposing the first electrode corresponding to the first dent portion and a second opening exposing the second electrode corresponding to the second dent portion.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hae Young Yun, Jun Young Kim, Jung-Hyun Cho
  • Patent number: 9818969
    Abstract: An OLED display device includes a driving semiconductor layer on a substrate, a gate insulating layer covering the driving semiconductor layer, a driving gate electrode and etching preventing layer on the gate insulating layer, a passivation layer on the gate insulating layer, driving gate electrode, and etching preventing layer, and including a plurality of protruding and depressed patterns, driving source and drain electrodes on the passivation layer, a pixel electrode on the protruding and depressed pattern, and exposed etching preventing layer, the pixel electrode having a protruding and depressed shape, a pixel definition layer on the passivation layer, and the driving source and drain electrodes, and having a pixel opening exposing the pixel electrode, an organic emission layer on the exposed pixel electrode, and a common electrode on the organic emission layer and pixel definition layer. The protruding and depressed pattern partially exposes the etching preventing layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung Hoon Park, Sun Park, Chun Gi You
  • Patent number: 9812335
    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-Woo Han, Junho Yoon, Kyohyeok Kim, Dongchan Kim, Sungyeon Kim, Jaehong Park, Jinyoung Park, KyungYub Jeon
  • Patent number: 9765430
    Abstract: A plasma processing apparatus for alternately performing a first plasma processing step using first and second processing gases and a second plasma processing step using third and fourth processing gases. The apparatus includes: a processing container that has a dielectric window in a ceiling and removably accommodates a workpiece; an exhaust unit that evacuates the processing container; a processing gas supply unit that supplies the first, second, third, and fourth processing gases into the processing container; a first gas introduction unit including a top plate gas injection port, a dielectric window gas flow path, and a first external gas flow path; a second gas introduction unit including a sidewall gas injection port, a sidewall gas flow path, and a second external gas flow path; an electromagnetic wave supply unit that supplies electromagnetic waves into the plasma generating space; a bypass exhaust path; and an opening/closing valve.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 19, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takehisa Saito, Takenao Nemoto, Koji Yamagishi, Hiroshi Kaneko
  • Patent number: 9768412
    Abstract: A composition which can be used as an organic water/oxygen barrier material, an OLED display device and manufacturing method thereof are disclosed. The composition includes: 15-25 wt % of parylene, 15-25 wt % of polyvinyl chloride, 5-15 wt % of acetone, 5-15 wt % of trichloroethylene, 10-20 wt % of polyvinyl acetate, 5-15 wt % of polyvinyl alcohol, 0-5 wt % of SiO2 nanoparticles, and 8-12 wt % of an organic solvent, wherein all weight percent values are based on the total weight of the composition. When a water/oxygen barrier layer fabricated by the composition is disposed between a luminescent layer of OLED and a light extraction layer, water vapor and oxygen gas can be prevented from entering the OLED luminescent layer, thereby prolonging the service life of the OLED luminescent layer.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: September 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Haidong Wu
  • Patent number: 9768414
    Abstract: A display device is provided. The display device includes a first substrate, a first barrier layer disposed on the first substrate, a second substrate, a second barrier layer disposed on the second substrate, an display medium disposed between the first barrier layer and the second barrier layer, and a metal enclosing wall connecting the first substrate to the second substrate and surrounding the display medium. The metal enclosing wall includes a first metal layer having a first opening and connected to the first substrate, a second metal layer connected to the second substrate, and a third metal layer formed between the first metal layer and the second metal layer.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: September 19, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Chi-Che Tsai, Po-Ching Lin, Wei-Yen Wu, Hui-Chen Hsu
  • Patent number: 9711579
    Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor disposed on the substrate, a first electrode disposed on the thin film transistor and electrically connected to the thin film transistor, a first auxiliary layer disposed on the first electrode, an emission layer disposed on the first auxiliary layer, an electron transport layer disposed on the emission layer, a first buffer layer disposed on the electron transport layer, and a second electrode disposed on the first buffer layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Il Soo Oh, Chang Ho Lee, Ji Hwan Yoon, Dae Yup Shin, Hee Joo Ko, Se Jin Cho, Jin Young Yun, Bora Lee, Yeon-Woo Lee, Beom Joon Kim, Pyung Eun Jeon, Hyun Ju Choi, Joong Won Sim, In Jae Lee
  • Patent number: 9685386
    Abstract: The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 20, 2017
    Assignee: CSME TECHNOLOGIES FAB1 CO., LTD.
    Inventor: Xiaodong He
  • Patent number: 9670058
    Abstract: An integrated circuit includes a mechanical device for detection of spatial orientation and/or of change in orientation of the integrated circuit. The device is formed in the BEOL and includes an accommodation whose sides include metal portions formed within various metallization levels. A mobile metal component is accommodated within the accommodation. A monitor inside the accommodation defines a displacement area for the metal component and includes electrically conductive elements disposed at the periphery of the displacement area. The component is configured so as to, under the action of the gravity, come into contact with the two electrically conductive elements in response to a given spatial orientation of the integrated circuit. A detector is configured to detect an electrical link passing through the component and the electrically conductive elements.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 6, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Antonio Di-Giacomo, Pascal Fornara
  • Patent number: 9653663
    Abstract: A package for multiple LED's and for attachment to a substrate includes a body, which includes a top body layer, a cavity disposed through the top body layer and having a floor for bonding to the multiple LED's, and a thermal conduction layer bonded to the top body layer and having a top surface forming the floor of the cavity and a bottom surface. The thermal conduction layer includes a thermally conducting ceramic material disposed between the floor and the bottom surface. The package also includes a plurality of LED bonding pads in direct contact with the floor and configured to bond to the multiple LED's and a plurality of electrical bonding pads in direct contact with the floor, proximate to the LED bonding pads, and in electrical communication with a plurality of electrical contacts disposed on a surface of the body.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 16, 2017
    Assignee: LedEngin, Inc.
    Inventor: Xiantao Yan
  • Patent number: 9647032
    Abstract: The present invention is directed to a spin-orbitronics device including a magnetic comparison layer structure having a pseudo-invariable magnetization direction; a magnetic free layer structure whose variable magnetization direction can be switched by a switching current passing between the magnetic comparison layer structure and the magnetic free layer structure; an insulating tunnel junction layer interposed between the magnetic comparison layer structure and the magnetic free layer structure; and a non-magnetic transverse polarizing layer formed adjacent to the magnetic comparison layer structure. The pseudo-invariable magnetization direction of the magnetic comparison layer structure may be switched by passing a comparison current through the transverse polarizing layer along a direction that is substantially parallel to a layer plane of the transverse polarizing layer. The pseudo-invariable magnetization direction of the magnetic comparison layer structure is not switched by the switching current.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 9, 2017
    Assignee: Avalanche Technology, Inc.
    Inventors: Xiaobin Wang, Parviz Keshtbod, Kimihiro Satoh, Zihui Wang, Huadong Gan
  • Patent number: 9620487
    Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: April 11, 2017
    Assignee: Apple Inc.
    Inventors: Kapil V. Sakariya, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 9620641
    Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Ali Khakifirooz, Alexander Reznicek, Soon-Cheon Seo