Abstract: A semiconductor device with technology for externally deciding if the stress test was performed or not. A semiconductor device includes a stress test circuit and a stress test decision circuit. The stress test circuit outputs control signals for executing the stress test to the stress test decision circuit and the object for testing. The stress test decision circuit then outputs the decision results if the stress test was performed, based on the control signals.

Abstract: An apparatus and a method for measuring an effective channel. The apparatus includes an automatic measurement system including a testing terminal for a substrate, a switching matrix disposed at one side of the automatic measurement system, a leakage current measuring device and a capacitance measuring device electrically connected to the switching matrix by a predetermined terminal, and a controller which controls the automatic measurement system, the leakage current measuring device, and the capacitance measuring device.

Abstract: A method of measuring on-resistance in a backside drain wafer includes providing a wafer having a first MOS transistor and a second MOS transistor each having a source and also sharing a drain provided at a backside of the wafer, and then forming a current flow path passing through the first and second MOS transistors, and then measuring a resistance between the sources of the first and second MOS transistors. Accordingly, an on-resistance in a backside drain wafer can be measured without using a chuck.

Abstract: A system for testing a flat panel display having a flat display panel assembly includes a testing stage for arranging the flat display panel assembly, a measuring apparatus being disposed on the testing stage and for measuring a spectrum of a transmitted light passing through a measuring region of the flat display panel assembly from a light source, a transporting apparatus for moving the measuring apparatus at a constant acceleration on the testing stage, a defect informing apparatus being electrically connected to the measuring apparatus and for informing an existence of defect, a type of defect, and a severity of defect by processing an electrical signal of the spectrum transmitted from the measuring apparatus.

Abstract: A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.

Abstract: An internal precision oscillator (IPO) is trimmed within a microcontroller integrated circuit. The microcontroller integrated circuit receives a test program into flash memory on the microcontroller integrated circuit from a tester. The microcontroller integrated circuit also receives a reference signal from the tester. The IPO generates a clock signal having a frequency that depends upon a trim value. A general purpose timer on the microcontroller integrated circuit counts the number of cycles of the clock signal during a time period defined by the reference signal and outputs a digital value. A processor on the microcontroller integrated circuit executes the test program, reads the digital output, and adjusts the trim value such that the frequency of the clock signal is calibrated with respect to the reference signal. Test-time on the tester is reduced because the decision making during the frequency trimming process is made by the processor instead of the tester.

Abstract: The invention relates to a testing apparatus for 4-wires resistive touch panel of an electronic system. The testing apparatus includes a voltage control unit, a signal control unit, a connecting unit and a determining unit. The determining unit is used for determining the connection of a first electronic unit and a second electronic unit according to a first voltage level and a second voltage level generated by the voltage control unit and a detecting signal generated by the signal control unit.

Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the lines of wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals. The connection section may include a performance board to which the device under test is mounted, where the lines of wiring are connected with each other on the performance board.

Abstract: Contact pressure between a wafer and a probe is maintained at an appropriate level. A probe card 2 has a contactor 11 for supporting a probe 10, a printed wiring board 13 electrically connected to the contactor 11, and a reinforcement member 14. On the upper surface side of the probe card 2 is provided a top plate 70 connected to the reinforcement member 14 by a connection member 80. A groove 90 is formed in the upper surface of the top plate 70, and a strain gauge 91 is attached at the groove 90. When a wafer W and the probe 10 are in contact with each other, an upward load acts on the probe card 2 by pressure caused by the contact, and the load causes strain in the top plate 70. The amount of the strain in the top plate 70 is measured, and contact pressure between the wafer W and the probe 10 is regulated and set based on the amount of the strain.

Abstract: An internal connection output pad (14A) connected to a CMOS output circuit (15A, 16A) on a first chip (11A) is electrically connected via a chip-to-chip bonding wire (17) to an internal connection input pad (14B) connected to a CMOS input circuit (15B, 16B) on a second chip (11B). In order to inspect the presence or absence of leakage resistance (40), a test circuit (30) controls a high-impedance output state, a high-level output state and a low-level output state of the internal connection output pad (14A) via the CMOS output circuit (15A, 16A). If a difference between a value obtained by measuring a current flowing through a power supply to a ground in the high-impedance output state and a value obtained by measuring such a current in the high-level output state is calculated, a transistor leakage current is canceled, so that a correct minute leakage current can be detected.

Abstract: Provided is a power supply circuit that supplies an electronic device with a supply power, including a voltage control section that outputs a control voltage that tracks an input voltage with a prescribed frequency characteristic and applies a voltage corresponding to the control voltage to the electronic device, a voltage adjusting section that detects the voltage applied to the electronic device and adjusts the input voltage based on the detected voltage, a current adjusting section that detects a current applied to the electronic device and adjusts the input voltage when the detected current is outside of a prescribed limit range, and a frequency characteristic adjusting section that increases a speed at which the control voltage tracks the input voltage by adjusting the frequency characteristic of the voltage control section when the applied current is outside of the limit range.

Abstract: Failure analysis method includes performing fixed radiation of semiconductor chip (wafer) by photocurrent generation laser beam, scanning and radiating a region to be observed on semiconductor chip by heating laser beam, detecting, by a SQUID fluxmeter, current change generated in the semiconductor chip by radiating the photocurrent generation laser beam and the heating laser beam, and analyzing failure of the semiconductor chip based on current change detected by the SQUID fluxmeter. Radiation of photocurrent generation laser beam and heating laser beam are performed from a back surface side of the LSI chip, and detection by the SQUID fluxmeter is performed on a front surface side of the LSI chip. In analysis of failure of the LSI chip, image processing is performed in which a signal outputted from the SQUID fluxmeter is made to correspond to a scanning point. Visualization of defects is possible.

Abstract: A mechanical support configuration for a probe card of a wafer test system is provided to increase support for a very low flexural strength substrate that supports spring probes. Increased mechanical support is provided by: (1) a frame around the periphery of the substrate having an increased sized horizontal extension over the surface of the substrate; (2) leaf springs with a bend enabling the leaf springs to extend vertically and engage the inner frame closer to the spring probes; (3) an insulating flexible membrane, or load support member machined into the inner frame, to engage the low flexural strength substrate farther away from its edge; (4) a support structure, such as support pins, added to provide support to counteract probe loading near the center of the space transformer substrate; and/or (5) a highly rigid interface tile provided between the probes and a lower flexural strength space transformer substrate.

Abstract: A method and system for monitoring and compensating the performance of an operational circuit is provided. The system includes one or more integrated circuit chips and a controller. Each integrated circuit chip includes one or more operational circuits, each operational circuit having at least one controllable circuit parameter. Each integrated circuit chip also includes a process monitor module at least partially constructed thereon. The controller is coupled to each process monitor module and to each operational circuit. The controller includes logic for evaluating the performance of an operational circuit based on data obtained from process monitor module and operational circuit related data stored in a memory. Based on the evaluation, the controller determines whether any deviations from desired or optimal performance of the circuit exist. If deviations exist, the controller generates a control signal to initiate adjustments to the operational circuit to compensate for the deviations.

Abstract: Provided is a test apparatus that tests a device under test, including a first pipeline that sequentially propagates pieces of pattern data included in a first test pattern, according to a first test period, and outputs the resulting data to the device under test; a second pipeline that sequentially propagates pieces of pattern data included in a second test pattern, according to a second test period that is different from the first test period, and outputs the resulting data to the device under test; a timing control section that controls at least one of a timing at which the first pipeline begins propagating a predetermined first pattern data and a timing at which the second pipeline begins propagating a predetermined second pattern data, based on the first test period and the second test period; and a judging section that judges pass/fail of the device under test based on a signal output by the device under test.

Abstract: Provided is a semiconductor device, in which: patterns for detecting displacement at probing are formed of a plurality of minute conductors formed below a protective film; each of the plurality of minute conductors formed below the protective film is electrically insulated and formed to be smaller than a bottom surface of a tip of a probing needle used for carrying out an electrical measurement of IC chips; and the patterns for detecting displacement at probing are provided in a pair for each of the IC chips.

Abstract: A test apparatus and device under test has a probe that can be located very close to contact pads and that requires very few solder connections. In addition, the probe can be configured to meet any appropriate and desired electrical specification while still using a same circuit board. There is no need to attach discrete components to a circuit board. Thus, by using a configurable probe, a single circuit board may be used with multiple probes or a reconfigurable probe to test for compliance with a variety of different electrical specifications having different requirements.

Abstract: There is provided a detector for detecting a layer short of a field winding in operation by measuring, with a field detector, a magnetic field generated from a field winding of an electric rotating machine. In the present invention, a field detector is installed outside an electric rotating machine to measure a leakage flux at the installation point to detect layer short by detecting the increase in a leakage flux or asymmetry of waveform of the leakage flux at an occurrence of a layer short of a field winding thereof, simplifying installation and enabling installation without halting operations of an electric rotating machine.

Abstract: Methods and apparatus provide for: selectively supplying a first source of power to a plurality of circuit blocks of a system using a plurality of gate circuits responsive to respective control signals provided by at least one control circuit; and providing a second source of power to operate the control circuit before the first source of power is available to the gate circuits such that the control signals are valid before such availability.

Abstract: A sampling module, for sampling one or more analog characteristics of a power transmission system, including at least one input circuit for sampling a respective analog characteristic. Each input circuit includes: a scaling circuit for reducing the magnitude of the analog characteristic to a desired level; an isolating circuit for creating an electrical barrier between respective upstream and downstream portions of the input circuit; and an analog to digital converter for digitizing the analog characteristic to produce a digital data stream. The scaling circuit is electrically connected to an input of the analog to digital converter, and the isolating circuit is electrically connected directly to an output thereof.