Patents Examined by Enamul M Kabir
  • Patent number: 10732894
    Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 4, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 10713136
    Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 14, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Fahad Ahmed, Chulmin Jung, Sei Seung Yoon, Esin Terzioglu
  • Patent number: 10715184
    Abstract: Methods and systems for improving the read and write performance of a distributed file system while limiting memory usage are described. The type of error correcting scheme applied to data, the partitioning of the data into data chunks, and the sizes of data slices within each of the data chunks used for storing electronic files within the distributed file system may be dynamically adjusted over time to optimize for fast IO performance while limiting memory usage (e.g., requiring less than 256 MB of RAM to generate and store code blocks). The file size of an electronic file to be stored, the amount of available memory for generating code blocks, and the amount of available disk space to store the electronic file may be used to set the data sizes of the data slices and the type of erasure code applied to data blocks associated with the data slices.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 14, 2020
    Assignee: RUBRIK, INC.
    Inventors: Arijit Banerjee, Garvit Juniwal, Adam Gee
  • Patent number: 10694506
    Abstract: To improve throughput by reducing the resource used for transmitting a parameter relating to retransmission control and decreasing overhead of retransmission control signaling. Where a retransmission control method is employed with adaptive MCS control in which the encoding rate can be changed, the scheduling section sets the MCS in accordance with CQI notified from the communication counterpart apparatus. When transmission data is encoded, the RV parameter bit-number setting section sets the number of bits used for signaling the RV parameter to decrease as the encoding rate of the first transmission is decreased and sets the RV parameter based on the number of bits. For example, in a case where the encoding rate R is R>?, two bits are set. In a case where the encoding rate ?<R??, one bit is set. On the other hand, in a case where R??, zero bits is set.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 23, 2020
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Masayuki Hoshino, Katsuhiko Hiramatsu, Yasuaki Yuda
  • Patent number: 10680722
    Abstract: A terminal in a communication system is provided. The terminal includes a transmitter configured to transmit a data frame including one preamble and a plurality of data blocks to another terminal by considering whether a preset signal is received, and a receiver configured to detect the preset signal from a signal received through an antenna while the data frame is transmitted by the transmitter.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-Suk Ko, Dae-Young Lee, Ohyun Jo, Jae-Hwa Kim
  • Patent number: 10680647
    Abstract: Techniques are described for performing a check node update (CNU) as part of iterative decoding of a low density-parity check (LDPC) code. The CNU uses a min-sum decoding approach that monitors whether two values received in messages from two variable nodes connected to a check nodes are equal and are the minimum value among the values received by the check nodes from other variable nodes connected thereto. Upon detecting such an event, the minimum value is adjusted by reducing it by an adjustment value to generate an adjusted minimum value. This adjusted minimum value approximates the minimum value that a sum-product algorithm (SPA) decoding approach would have generated. The adjusted minimum value is included in a response message sent from the check node to a variable node. The bit corresponding to that variable node is decoded based on this adjusted minimum value.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Naveen Kumar, Abhiram Prabhakar, Chenrong Xiong, Fan Zhang
  • Patent number: 10572158
    Abstract: A storage device may include a plurality of memory cells arranged in pages and blocks, each page including a row of memory cells, and each block including a plurality of pages of memory cells. The storage device may include a memory device, such as a nonvolatile memory device, which includes these items. A data recovery method for the storage device may include receiving by the storage device a first command corresponding to a first selected data recovery scheme. Based on the first command: a first target page scheme for performing error detection on the plurality of blocks is applied, target pages are read using the first target page scheme, and an amount of errors in each read target page is detected. In addition, it may be determined that a target page of a first block has at least a first threshold amount of errors, and based on the determination, data recovery for the first block may be performed by relocating all data stored in the first block to another block.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONCIS CO., LTD.
    Inventors: Sang Yong Lee, Shin Wook Gahng, Chul Lee
  • Patent number: 10574264
    Abstract: The disclosure discloses a method for supporting low bit rate coding. A source data packet to be coded is repeated for i times, and the data packet which is repeated for i times is coded. The disclosure also discloses an apparatus for supporting low bit rate coding and a computer storage medium.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: February 25, 2020
    Assignee: ZTE Corporation
    Inventors: Liguang Li, Jun Xu, Zhifeng Yuan, Jin Xu, Kaibo Tian, Jun Zhang, Haiming Wang, Shiwen He
  • Patent number: 10541780
    Abstract: Various features pertain to mitigating interference on downlink/uplink channels caused by bursty traffic transmissions. A transmitting node encodes data into transport blocks, each including code blocks in which the data is encoded. The transport blocks are then wirelessly transmitted over a channel specific to a receiving node, where the code blocks of the transport blocks are transmitted without redundant parity code blocks or with a desired amount of redundant parity code blocks. The transmitting node then receives an indication from the receiving node of a number of failed data code blocks. The transmitting node generates an error correction code sufficient to recover all of the failed code blocks and transmits the error correction code within a new transport block along with new data.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: January 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Krishna Kiran Mukkavilli, Jing Jiang, Naga Bhushan, Joseph Binamira Soriaga, Tingfang Ji, Kambiz Azarian Yazdi, Santosh Paul Abraham, John Edward Smee
  • Patent number: 10528421
    Abstract: Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: January 7, 2020
    Assignee: ARTERIS, INC.
    Inventors: Monica Tang, Xavier van Ruymbeke
  • Patent number: 10521296
    Abstract: A data block may be identified. A first decoding operation may be performed on the data block. An unsuccessful correction of an error of the data block associated with the first decoding operation may be determined. A set of bits of the data block that caused the unsuccessful correction of the error of the data block may be identified. In response to identifying the set of bits of the data block that is associated with the unsuccessful correction of the error, a second decoding operation on the set of bits of the data block may be performed. The second decoding operation may be different than the first decoding operation.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 31, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yingquan Wu, Eyal En Gad
  • Patent number: 10521134
    Abstract: A memory system has a first memory which comprises a nonvolatile memory data region, and a second memory which stores data before storing in a third memory, the data not being written back on the third memory in a lower-level with access priority lower than access priority of the first memory, among data inside the nonvolatile memory data region, wherein the second memory has a bit error rate lower than a bit error rate of the first memory.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: December 31, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 10509695
    Abstract: Detection of abnormalities in HDBD is performed by processing it to obtain a dictionary from a training data. This is done by computing a low rank randomized LU decomposition which enables constant online updating of the training data and thus gets constant updating of the normal profile in the background.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: December 17, 2019
    Assignee: ThetaRay Ltd.
    Inventors: Amir Averbuch, Gil Shabat, Yaniv Shmueli
  • Patent number: 10504566
    Abstract: The method of operating a storage device includes receiving a command, an address, and data, and comparing data previously stored at a storage space of the nonvolatile memory corresponding to the address with the received data in response to the command. The method includes writing the received data at a nonvolatile memory when the previously stored data is different from the received data. Writing of the received data is terminated when the previously stored data is equal to the received data.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Juhyung Hong
  • Patent number: 10498359
    Abstract: Correction data units for data packets of a data stream are generated. A correction data unit is based on a set of the data packets of the stream. The stream is transmitted over a lossy communication channel. A performance measure to be optimized is selected, which relates to the recovery of lost data packets of the stream. A coding requirement is determined. For the generation of the correction data units, it is determined, within the constraints of the coding requirement and based on previously generated correction data units, which of the data packets in the stream to include in the set on which the generation of the correction data unit is to be based to thereby optimize the selected performance measure. A generated correction data unit is generated based on a respective set of the data packets of the stream. The generated correction data units are included in the stream.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: December 3, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Renat Vafin, Soren Vang Andersen, Mattias Nilsson
  • Patent number: 10489240
    Abstract: A file system can allocate data of a storage system into data units, wherein a set of data units can be grouped into a storage region within a volume. A process of verifying validity of data within a storage region can include obtaining a first set of error-detecting codes from a subset of the data stored in a storage system, such as from a data unit of a file system object. Each of the first set of error-detecting codes can be associated with a corresponding data unit within the storage region. A second set of error-detecting codes can be generated based at least in part on the first set of error-detecting codes, and the second set of error-detecting codes can be associated with the storage region so that the second set of error-detecting codes can be used to verify the validity of the data within the storage region.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: November 26, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Cornel Emilian Rat, William Tipton, Chesong Lee, Rajsekhar Das, Erik Hortsch, Arushi Aggarwal
  • Patent number: 10476634
    Abstract: Systems and methods for Polar encoding with a blockwise checksum are provided. The method involves processing a set of K information blocks to produce a blockwise checksum with u blocks, where K>=2, and u>=1, and where each information block or checksum block contains P bits. The blockwise checksum may, for example, be a Fletcher checksum. The Polar code may be based on an m-fold Kronecker product matrix. Then, an N-bit input vector is produced with P×K information bits and the P×u blockwise checksum bits, and with N?PK?Pu frozen bits, where N=2m where m>=2. The N-bit input vector is processed to produce a result equivalent to multiplying the input vector by a Polar code generator matrix to produce a codeword. The codeword is then transmitted or stored.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 12, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yiqun Ge, Wuxian Shi
  • Patent number: 10476529
    Abstract: An error detection code generation circuit of a semiconductor device includes a first cyclic redundancy check (CRC) engine, a second CRC engine and an output selection engine. The first CRC engine generates first error detection code bits using a first generation matrix, based on a plurality of first unit data and first DBI bits in response to a mode signal. The second CRC engine generates second error detection code bits using a second generation matrix, based on a plurality second unit data and second DBI bits, in response to the mode signal. The output selection engine generates final error detection code bits by merging the first error detection code bits and the second error detection code bits in response to the mode signal. The first generation matrix is the same as the second generation matrix.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: November 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Ye-Sin Ryu, Young-Sik Kim, Su-Yeon Doo
  • Patent number: 10467092
    Abstract: Providing space-efficient storage for dynamic random access memory (DRAM) cache tags is provided. In one aspect, a DRAM cache management circuit provides a plurality of cache entries, each of which contains a tag storage region, a data storage region, and an error protection region. The DRAM cache management circuit is configured to store data to be cached in the data storage region of each cache entry. The DRAM cache management circuit is also configured to use an error detection code (EDC) instead of an error correcting code (ECC), and to store a tag and the EDC for each cache entry in the error protection region of the cache entry. In this manner, the capacity of a DRAM cache can be increased by avoiding the need for the tag storage region for each cache entry, while still providing error detection for the cache entry.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Natarajan Vaidhyanathan, Mattheus Cornelis Antonius Adrianus Heddes, Colin Beaton Verrilli
  • Patent number: 10454499
    Abstract: Certain aspects of the present disclosure generally relate to techniques for enhanced puncturing and low-density parity-check (LDPC) code structure. A method for wireless communications by a transmitting device is provided. The method generally includes encoding a set of information bits based on a LDPC code to produce a code word, the LDPC code defined by a base matrix having a first number of variable nodes and a second number of check nodes; puncturing the code word according to a puncturing pattern designed to puncture bits corresponding to at least two of the variable nodes to produce a punctured code word; adding at least one additional parity bit for the at least two punctured variable nodes; and transmitting the punctured code word.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 22, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar