Abstract: An Ethernet power sourcing equipment (PSE), and a method and an apparatus for power over Ethernet (PoE), where the Ethernet PSE includes a PSE chip, a master control processor, a power supplying port, and a preprocessor. The preprocessor is configured to determine whether the master control processor starts upon power-on, control the PSE chip to detect whether the power supplying port is connected to a valid powered device (PD) when the master control processor starts upon power-on, and control, according to a preset rule, the PSE chip to power on the valid PD when the power supplying port is connected to the valid PD. Hence, the Ethernet PSE has abundant management functions and can quickly power on a PD.

Abstract: Techniques to inspect packets to determine a destination node are provided. In one aspect, a Wake on Lan (WOL) packet may be received at a switch. A destination node of the WOL packet may be determined. An indication of the determined destination node may be sent to a management controller. The management controller may cause the destination node to awaken.

Abstract: Disclosed are various embodiments securing the execution of unauthorized applications on a computing device. A file system stored in a storage device includes files and file system data structures. The file system data structures have kernel space accessible portions. When a file is executed, a computing device can determine whether the file can be executed based on a file system data structure corresponding to the file based on the kernel space accessible portion. The operating system can determine whether to execute the file or take another action based on flags stored in the kernel space accessible portion.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Abstract: A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in other architectural mode of the plurality of architectural modes, wherein the other architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the other architectural mode in place of the one architectural mode restricting use of the one architectural mode.

Abstract: A determination is made that a configuration architectural mode facility is installed in a computing environment that is configured for a plurality of architectural modes and has a defined power-on sequence that is to power-on the computing environment in one architectural mode of the plurality of architectural modes. Based on determining that the configuration architectural mode facility is installed, the computing environment is reconfigured to restrict use of the one architectural mode. The reconfiguring includes selecting a different power-on sequence to power-on the computing environment in another architectural mode of the plurality of architectural modes, wherein the another architectural mode is different from the one architectural mode, and executing the different power-on sequence to power-on the computing environment in the another architectural mode in place of the one architectural mode restricting use of the one architectural mode.

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract: A computer system includes a power supply unit that provides operating energy for the computer system, a system board connected to the power supply unit and having a multitude of expansion connections for connection of a corresponding multitude of expansion components, wherein each expansion component is assigned a fixed power budget to supply an associated expansion component, a first expansion component connected to a first expansion connection of the system board, and at least one auxiliary supply component arranged in a region of a second expansion connection of the system board, wherein the auxiliary supply component electrically connects to the first expansion component and delivers at least part of the power budget assigned to the second expansion connection to the first expansion component.

Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract: Techniques for detecting an early boot error are provided. In one aspect, a host processor may transition to a first phase of an early boot process. The early boot process may occur before the host processor initializes a primary link between the host processor and a management controller. The host processor may then update a dual purpose boot register to store an early boot phase identifier corresponding to the first phase and an early boot status identifier corresponding to the first phase.

Abstract: An apparatus for processing data 2 contains multiple power domains which may be in a non-retaining power state or a retaining power state. If a power domain is in a non-retaining power state in which it is not able to retain a copy of a stored parameter value and it is switched into a retaining power state in which it requires a copy of that parameter value, then it fetches the parameter value from a store within another power domain. One of the power domains contains a master copy of the parameter value to which writes changing in the parameter value are made. At least one of the other power domains fetches a copy of the parameter value if required from a power domain other than the power domain containing the master copy.

Abstract: Techniques for managing energy use of a computing deployment are provided. In one embodiment, a computer system can establish a performance model for one or more components of the computing deployment, where the performance model models a relationship between one or more tunable parameters of the one or more components and an end-to-end performance metric, and where the end-to-end performance metric reflects user-observable performance of a service provided by the computing deployment. The computer system can further execute an algorithm to determine values for the one or more tunable parameters that minimize power consumption of the one or more components, where the algorithm guarantees that the determined values will not cause the end-to-end performance metric, as calculated by the performance model, to cross a predefined threshold. The computer system can then enforce the determined values by applying changes to the one or more components.

Abstract: One embodiment provides a method, including: executing, using at least one processor, computer readable program code to: identify a plurality of possibilities at the disposal of a data center for changing its energy demand in its role as a consumer of energy, wherein each of the possibilities is associated with: a time interval during which change in energy consumption of the data center is to take place; and an amount of energy to be drawn, during the time interval, by the data center from an electric provider through a connection to a power grid; wherein the plurality of possibilities are different from each other; proactively determine, based on the identified plurality of possibilities, the ability of the data center to change its energy consumption, thereby changing the amount of energy drawn by the data center from the energy provider; and communicate, to a remote device that is in direct communication with an energy supplier, data indicating the ability of the data center to change its energy consumpti

Abstract: Embodiments are described for dynamically responding to demand for server computing resources. The embodiments can monitor performance of each of multiple computing systems in a data center, identify a particular computing system of the multiple computing systems for allocation of additional computing power, determine availability of an additional power supply to allocate to the identified computing system, determine availability of a capacity on a power distribution line connected to the particular computing system to provide the additional power supply to the particular computing system, and allocate the additional computing power to the identified computing system as a function of the determined availability of the additional power supply and the determined availability of the capacity on the power distribution line.

Abstract: Device drivers are provided from virtual media. System resources trap input/output data associated with the device drivers. Memory is allocated for the virtual media and populated with the device drivers using the input/output data. As an operating system installs, the virtual media is readable and is accessed for the device drivers.

Abstract: In a system using a device not adapted to a single wire bus, a semiconductor device includes an external terminal to be coupled to a power source terminal of an external device, a port that supplies a power source voltage for the external device to the external terminal, a power manager that controls an output of the port, and a CPU that controls an operation of the power manager.

Abstract: A method may include associating, with a timer-B, a second application in a terminal device; setting the terminal device in a standby mode; and executing the second application when a processor in the terminal device wakes up after the timer-B measures a second amount of elapsed time. The timer-B may not initiate wake-up of the processor. The method may further include determining whether the second application is associated with the timer-B or a timer-A when the terminal device receives a command of setting the terminal device in the standby mode; and when the second application is determined as being associated with the timer-A, unassociating the second application with the timer-A. The timer-A may initiate wake-up of the processor when the timer-A measures another second amount of elapsed time while the terminal device is the standby mode. A timer associated with a first application may initiate wakeup of the processor.

Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.