Abstract: A semiconductor device includes a gate stack with conductive layers and insulating layers that are stacked alternately with each other, a first channel pattern passing through the gate stack, a second channel pattern coupled to the first channel pattern, the second channel pattern protruding above a top surface of the gate stack, an insulating core formed in the first channel pattern, the insulating core extending into the second channel pattern, a gate liner with a first portion that surrounds a top surface of the gate stack and a second portion that surrounds a portion of a sidewall of the second channel pattern, and a barrier pattern coupled to the gate liner, the barrier pattern surrounding a remaining portion of the sidewall of the second channel pattern.

Abstract: An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.

Abstract: A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

Abstract: Provided is a display apparatus. The display apparatus comprises a substrate including a display area, a first component area where first pixel groups including first auxiliary sub-pixels and first transmitting portions are located, and a second component area where second pixel groups including second auxiliary sub-pixels and second transmitting portions are located, first display elements, and second display elements, wherein one of the first pixel groups is spaced apart by a first distance in a first direction from a first center of the first component area, and is spaced apart by a second distance in a second direction intersecting the first direction from the first center, and one of the second transmitting portions is spaced apart by the first distance in the first direction from a second center of the second component area, and is spaced apart by the second distance in the second direction from the second center.

Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

Abstract: The present invention discloses a micro light emitting diode display substrate and a manufacturing method thereof. The substrate includes an underlay substrate, a thin film transistor and a micro light emitting diode disposed on a top surface of the underlay substrate and connected to each other, a first metal film layer disposed on a bottom surface of the underlay substrate and at least formed with fanout circuit pattern and a side printed bonding pad. The fanout circuit pattern is connected to the side printed bonding pad, the side printed bonding pad is connected to the thin film transistor through a side wire such that after the display substrate is assembled with a bezel, a top surface display pixel region can maximally approach the bezel, to achieve bezel-less effect.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion cut for gate structures and methods of manufacture. The structure includes: a plurality of fin structures; a plurality of gate structures extending over the plurality of fin structures; a plurality of diffusion regions adjacent to the each of the plurality of gate structures; a single diffusion break between the diffusion regions of the adjacent gate structures; and a liner separating the single diffusion break from the diffusion regions.

Abstract: The present inventions, in one aspect, are directed to micromachined resonator comprising: a first resonant structure extending along a first axis, wherein the first axis is different from a crystal axis of silicon, a second resonant structure extending along a second axis, wherein the second axis is different from the first axis and the crystal axis of silicon and wherein the first resonant structure is coupled to the second resonant structure, and wherein the first and second resonant structures are comprised of silicon (for example, substantially monocrystalline) and include an impurity dopant (for example, phosphorus) having a concentrations which is greater than 1019 cm?3, and preferably between 1019 cm?3 and 1021 cm?3.

Abstract: A display device includes a substrate, pixels each including at least one transistor, a storage capacitor connected to the at least one transistor, and a light emitting element connected to the at least one transistor, scan lines connected to each of the pixels, a data line connected to each of the pixels, and a power line supplying a first power voltage to the light emitting element. The power line includes a first conductive pattern that extends in a first direction, and is provided on a first insulating interlayer, a second conductive pattern that extends in the first direction, is provided on a second insulating interlayer, and is connected to the first conductive pattern through a first contact hole, and a third conductive pattern that extends in a second direction, is provided on a third insulating interlayer, and is connected to the second conductive pattern through a second contact hole.

Abstract: Provided in the present application is a pixel structure. The pixel structure includes a plurality of pixel units. Each of the pixel units includes four sub-pixels, and the four sub-pixels are one first sub-pixel, two second sub-pixels, and one third sub-pixel, respectively. The two second sub-pixels share a common side to form a second sub-pixel unit. The first sub-pixel and the third sub-pixel are disposed at two opposite sides of the second sub-pixel unit, respectively. And each of the pixel units has a shape of a triangle. Also provided in the present application is a display panel.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a normal display region and a functional region. The normal display region includes a first display region, a second display region and a third display region. Along a first direction, lengths of third, first and second display regions of the normal display region decrease. One of the first and third display regions is a specific display region where first semiconductor pattern layers are located. The first semiconductor pattern layers are arranged along a third direction and connected to each other. In the second display region, the second semiconductor pattern layers first semiconductor pattern layers is arranged along a third direction and connected to each other. The second semiconductor pattern layers are connected to the first semiconductor pattern layers.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes: a base substrate including a display area and a border area around the display area; and a signal line and an electrode line located in the border area of the base substrate. The signal line is arranged in a same layer as a source-drain electrode layer in the display area, and the electrode line is arranged in a same layer as an anode layer in the display area. The electrode line is overlapped on a surface of the signal line away from the base substrate, overlapping surfaces of the signal line and the electrode line are two concave-convex surfaces fitted to each other.

Abstract: A field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure having: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the change extending from the upper surface of the gate into the region between gate and the drain; and wherein the electric charge solely produces the electric field.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

Abstract: High power transistors, such as high power gallium nitride (GaN) transistors, are described. These high power transistors have larger total gate widths than conventional high power transistors by arranging multiple linear arrays of contacts in parallel. Thereby, the total gate width and the power rating of a high power transistor may be increased without elongating the die of the high power transistor. Accordingly, the die of the high power transistor may be mounted in a smaller circuit package relative to conventional dies with the same power rating.

Abstract: In an embodiment, a device includes: an interconnect structure including a first contact pad, a second contact pad, and an alignment mark; a light emitting diode including a cathode and an anode, the cathode connected to the first contact pad; an encapsulant encapsulating the light emitting diode; a first conductive via extending through the encapsulant, the first conductive via including a first seed layer, the first seed layer contacting the second contact pad; a second conductive via extending through the encapsulant, the second conductive via including a second seed layer, the first seed layer and the second seed layer including a first metal; and a hardmask layer between the second seed layer and the alignment mark, the hardmask layer including a second metal, the second metal different from the first metal.

Abstract: A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.