Patents Examined by Eric T Loonan
  • Patent number: 10860474
    Abstract: In an example, a starting address corresponding to a location of particular information within a non-volatile storage memory is determined during an initialization process using a multilevel addressing scheme. Using the multilevel addressing scheme may include performing multiple reads of the storage memory at respective address levels to determine the starting address corresponding to the location of the particular information.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gianfranco Ferrante, Dionisio Minopoli
  • Patent number: 10846001
    Abstract: A distributed storage schemes manages implementation of QoS targets for IOPs across compute nodes executing applications, primary storage nodes storing a primary copy of a logical storage volume, and clone storage nodes. On the compute node, a maximum priority is assigned to a minimum number of IOPs in a queue within a time window from a time of receipt of a last unexecuted IOP. Other IOPs are assigned a minimum priority. On the storage node, maximum priority IOPs are assigned to high priority queues, from which IOPs are executed first, and low priority IOPs are assigned to low priority queues. Methods for determining the capacity of storage nodes and allocating storage requests are also disclosed.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 24, 2020
    Assignee: ROBIN SYSTEMS, INC.
    Inventors: Shravan Kumar Vallala, Dhanashankar Venkatesan
  • Patent number: 10846017
    Abstract: A non-volatile memory system accepts Secure Digital (SD) Commands and manages a data buffer that buffers data for the SD commands. The SD Commands may be accepted over an SD bus of the non-volatile memory system. The SD Commands may be accepted over a PCIe bus of the non-volatile memory system. The memory system may generate one or more NVMe commands for each SD command, and submit the NVMe command(s) to an NVMe submission queue. Upon completion all of the NVMe commands that were generated for an SD command, the memory system may report completion status of the SD command to an SD host. The memory system ensures that the timing requirements for SD commands are met even though a conversion from SD commands to NVMe commands may be performed. The memory system makes efficient use of the depth of the NVMe submission queue.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 24, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Agarwal
  • Patent number: 10831368
    Abstract: In one embodiment, a method for managing a local storage memory for a mobile device includes detecting a level of memory usage of the local storage memory of the mobile device rising above a first threshold. The method determines a respective portion of the level of memory usage of the local storage memory on a per software application basis for a plurality of software applications, and determines a user preference for a memory relief action. The method then implements the memory relief action for at least one software application of the plurality of software applications based on the user preference.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 10, 2020
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventor: Emmanuel O. Etuke
  • Patent number: 10817421
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a persistent data structure. A method includes associating a logical identifier with a data structure. A method includes writing data of a data structure to a first region of a volatile memory module. A volatile memory module may be configured to ensure that data is preserved in response to a trigger. A method includes copying data of a data structure from a volatile memory module to a non-volatile storage medium such that the data of the data structure remains associated with a logical identifier.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nisha Talagala, Swaminathan Sundararaman, David Flynn
  • Patent number: 10817502
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include providing a persistent data structure stored at least partially in volatile memory configured to ensure persistence of the data structure in a non-volatile memory medium. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality of supported interfaces is to be used to flush data from a processor complex.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nisha Talagala, Swaminathan Sundararaman, David Flynn
  • Patent number: 10817224
    Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: October 27, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Subrato Kumar De, Dexter Chun, Yanru Li
  • Patent number: 10817320
    Abstract: A method for improving accuracy of high resolution timers in a live partition migration comprises determining a status of each page of a plurality of pages to be copied from a source partition to a target partition during the live partition migration. One or more pages of the plurality of pages correspond to a respective high resolution timer. The method comprises determining that each of the one or more pages corresponding to a respective high resolution timer has a clean status. A clean status indicates that the corresponding page has been copied to the target partition and has not been modified subsequent to being copied to the target partition. The method also comprises halting operation of the source partition and initiating operation of the target partition in response to determining that each of the one or more pages corresponding to a respective high resolution timer has a clean status.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Brahadambal Srinivasan
  • Patent number: 10802712
    Abstract: To avoid the situation that only specific data in date corresponding to a plurality of data types occupies a temporary storing part. An interface control part 26 of a data processing processor 10 sets data type information according to a data type of data which is requested to read. A memory controller 46 of an auxiliary storage device 40 controls the auxiliary storage device 40 to determine the data type requested based on the data type information contained in a read command from the data processing processor 10 and select a temporary storing region corresponding to the data type.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 13, 2020
    Assignee: AXELL CORPORATION
    Inventors: Atsushi Obata, Kenta Matsumoto
  • Patent number: 10761756
    Abstract: A technique for performing in-line compression includes receiving data into a data log that temporarily holds the data and aggregating the data into batches, where each batch includes multiple blocks of received data. For each batch of data, a storage system performs a compression operation, which proceeds block-by-block, compressing each block and comparing a total compressed size of all blocks compressed so far against a budget. The storage system increments the budget for successive blocks, such that a per-block budget is greater for a first block in the batch than it is for a last block in the batch, thus allowing earlier blocks to meet budget even if they are relatively incompressible.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Ivan Bassov, Philippe Armangau, Yining Si
  • Patent number: 10761772
    Abstract: According to one embodiment, there is provided a memory system including a nonvolatile semiconductor memory, a bus, and a controller. The nonvolatile semiconductor memory includes a first chip and a second chip. The bus is connected to the first chip and the second chip in common. The controller issues a first command to the first chip via the bus. The controller queues a second command whose access destination is identified to be the first chip at a first timing while the first chip is executing the first command. The controller issues to the second chip a third command whose access destination is identified to be the second chip after the first timing, via the bus in priority over the second command, while the first chip is executing the first command or after the execution of the first command finishes.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 1, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Taro Iwashiro, Takuya Haga
  • Patent number: 10754813
    Abstract: Methods, apparatus, and computer-accessible storage media for optimizing block storage I/O operations in a storage gateway. A write log may be implemented in a block store as a one-dimensional queue. A read cache may also be implemented in the block store. When non-ordered writes are received, sequential writes may be performed to the write log and the data may be written to contiguous locations on the storage. A metadata store may store metadata for the write log and the read cache. Reads may be satisfied from the write log if possible, or from the read cache or backend store if not. If blocks are read from the read cache or backend store to satisfy a read, the blocks may be mutated with data from the write log before being sent to the requesting process. The mutated blocks may be stored to the read cache.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 25, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: James Christopher Sorenson, III, Yun Lin, Satish Kumar Kotha, Ankur Khetrapal
  • Patent number: 10725807
    Abstract: A hypervisor configures a page table entry in a host page table to map an address associated with memory-mapped input-output (MMIO) for a virtual device of a guest of the hypervisor to an input/output (I/O) instruction. The address is marked in the page table entry as a hypervisor exit entry, and the page table entry to cause an exit to the hypervisor responsive to the guest attempting to access the address. Responsive to detecting an exit to the hypervisor caused by the guest attempting to access the address, the hypervisor receives the I/O instruction mapped to the address that caused the exit. The hypervisor then executes the I/O instruction on behalf of the guest.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 28, 2020
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Paolo Bonzini
  • Patent number: 10712950
    Abstract: A system that implements a scalable data storage service may maintain tables in a data store on behalf of storage service clients. The service may maintain table data in multiple replicas of partitions that are stored on respective computing nodes in the system. In response to detecting an anomaly in the system, detecting a change in data volume on a partition or service request traffic directed to a partition, or receiving a service request from a client to split a partition, the data storage service may create additional copies of a partition replica using a physical copy mechanism. The data storage service may issue a split command defined in an API for the data store to divide the original and additional replicas into multiple replica groups, and to configure each replica group to maintain a respective portion of the table data that was stored in the partition before the split.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: July 14, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Stefano Stefani, Timothy Andrew Rath, Chiranjeeb Buragahain, Yan Valerie Leshinsky, David Alan Lutz, Jakub Kulesza, Wei Xiao, Jai Vasanth
  • Patent number: 10705961
    Abstract: A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Yen-Cheng Liu, Bahaa Fahim, Erik G. Hallnor, Jeffrey D. Chamberlain, Stephen R. Van Doren, Antonio Juan
  • Patent number: 10698463
    Abstract: A control unit included in a PLC generates power-cut retaining information to be retained at a power cut, and stores the generated power-cut retaining information into a main memory. The control unit includes a file system unit for reading and writing target information from and into a nonvolatile memory. When the file system unit receives a power cut notification indicating a cut of power fed while reading or writing target information from or into a nonvolatile memory, the file system unit stops the reading or writing process, and writes the power-cut retaining information stored in the main memory into the nonvolatile memory using power fed from the auxiliary power supply.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: June 30, 2020
    Assignee: OMRON Corporation
    Inventors: Takamasa Mioki, Mizuki Mori
  • Patent number: 10585623
    Abstract: A computer system includes a hardware buffer controller. Memory access requests to a buffer do not include an address within the buffer and threads accessing the buffer do not access or directly update any pointers to locations within the buffer. The memory access requests are addressed to the hardware buffer controller, which determines an address from its current state and issues a memory access command to that address. The hardware buffer controller updates its state in response to the memory access requests. The hardware buffer controller evaluates its state and outputs events to a thread scheduler in response to overflow or underflow conditions or near-overflow or near-underflow conditions. The thread scheduler may then block threads from issuing memory access requests to the hardware buffer controller. The buffer implemented may be a FIFO or other type of buffer.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: March 10, 2020
    Assignee: VIVANTE CORPORATION
    Inventor: Mankit Lo
  • Patent number: 10528276
    Abstract: Technical solutions are described that shift wearout of an array of storage disks in a storage system. In an aspect, a method includes receiving a request to write data to the storage system. The method also includes generating checksum data corresponding to the data and dividing the checksum data into portions of distinct sizes. The method also includes writing each portion of the checksum data onto a respective storage disk in the array.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffery M. Franke, James A. O'Connor
  • Patent number: 10528277
    Abstract: Technical solutions are described that shift wearout of an array of storage disks in a storage system. In an aspect, a method includes receiving a request to write data to the storage system. The method also includes generating checksum data corresponding to the data and dividing the checksum data into portions of distinct sizes. The method also includes writing each portion of the checksum data onto a respective storage disk in the array.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffery M. Franke, James A. O'Connor
  • Patent number: 10489293
    Abstract: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: November 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sanjeev Ghai, Guy Lynn Guthrie, Stephen Powell, William John Starke