Patents Examined by Eric T Oberly
  • Patent number: 11526285
    Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: December 13, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wei-Chen Wang, Hung-Sheng Chang, Chien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo
  • Patent number: 11526275
    Abstract: Systems and methods for sampling a set of block IDs to facilitate estimating an amount of data stored in a data set of a storage system having one or more characteristics are provided. According to an example, metadata (e.g., block headers and block IDs) may be maintained regarding multiple data blocks of the data set. When one or more metrics relating to the data set are desired, an efficiency set, representing a subset of the block IDs of the data set, may be created to facilitate efficient calculation of the metrics by statistically sampling the block IDs of the data set. Finally, the metrics may be estimated based on the efficiency set by analyzing one or more of the metadata (e.g., block headers) and the data contained in the data blocks corresponding to the subset of the block IDs and extrapolating the metrics for the entirety of the data set.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 13, 2022
    Assignee: NetApp, Inc.
    Inventors: Charles Randall, Alyssa Proulx
  • Patent number: 11501135
    Abstract: There is provided a smart engine including a profile collector and a main processing module. The profile collector is configured to store a plurality of profiles, one or more suitable profiles being dynamically selected according to an instruction from a user or an automatic selector. The main processing module is connected to the profile collector and directly or indirectly connected to a sensor, and configured to perform a detailed analysis to determine detailed properties of features, objects, or scenes based on suitable sensor data from the sensor.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 15, 2022
    Assignee: BRITISH CAYMAN ISLANDS INTELLIGO TECHNOLOGY INC.
    Inventors: Meng-Hsun Wen, Cheng-Chih Tsai, Jen-Feng Li, Hong-Ching Chen, Chen-Chu Hsu, Tsung-Liang Chen
  • Patent number: 11487436
    Abstract: Instructions can be executed to determine a quantity of logical units that are part of a memory device. The instructions can be executed to operate the logical units with a programming time sufficient to provide a required throughput for storage of time based telemetric sensor data received from a host. The instructions can be executed to operate the logical units with a trim that correspond to the programming time.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey S. McNeil, Jr., Niccolo' Righetti, Kishore K. Muchherla, Akira Goda, Todd A. Marquart, Mark A. Helm, Gil Golov, Jeremy Binfet, Carmine Miccoli, Giuseppina Puzzilli
  • Patent number: 11487691
    Abstract: A rack-mounted system includes a chassis, a switchless board disposed in the chassis, a midplane, and a plurality of device ports. The switchless board includes a baseboard management controller (BMC), a network repeater configured to transport network signals, and a PCIe switch configured to transport PCIe signals. Each of the plurality of device ports is configured to connect a storage device to the midplane and carry the network signals and the PCIe signals over the midplane. The storage device is configurable to operate in one of multiple storage protocol modes based on a type of the chassis. The network repeater of the switchless board is swappable with an Ethernet switch to provide a switching compatibility to the chassis using the same midplane. The storage device can operate in single-port and dual-port configurations.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sompong Paul Olarig, Fred Worley, Son Pham
  • Patent number: 11487440
    Abstract: Disclosed is an evaluation system for evaluating a resource operation of an information system by a user. The evaluation system includes one or more arithmetic units, and one or more storage devices. The one or more storage devices are configured to store risk management information for managing an erroneous operation risk evaluation index relating to the resource operation of the information system. The one or more arithmetic units are configured to: receive operation information indicating a first resource operation designated by a first user, and evaluate an erroneous operation risk of the first resource operation based on the first resource operation and the risk management information.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: November 1, 2022
    Assignee: HITACHI, LTD.
    Inventors: So Suzuki, Hiroshi Hayakawa
  • Patent number: 11481317
    Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example apparatus can include a plurality of computing devices. Each of the computing devices can include a processing unit configured to perform an operation on a block of data, and a memory array configured as a cache for each respective processing unit. The example apparatus can further include a first communication subsystem coupled to a host and to each of the plurality of communication subsystems. The example apparatus can further include a plurality of second communication subsystems coupled to each of the plurality of computing devices. Each of the plurality of computing devices can be configured to receive a request from the host, send a command to execute at least a portion of the operation, and receive a result of performing the operation from the at least one hardware accelerator.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vijay S. Ramesh, Allan Porterfield, Richard D. Maes
  • Patent number: 11481117
    Abstract: In some examples, a system assigns workload fingerprints to each respective storage volume of a plurality of storage volumes, the workload fingerprints assigned to the respective storage volume across a plurality of points. Based on the workload fingerprints assigned to respective storage volumes of the plurality of storage volumes, the system groups the storage volumes into clusters of storage volumes. The system manages an individual cluster of the clusters of storage volumes according to an attribute associated with the individual cluster.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: October 25, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mayukh Dutta, Manoj Srivatsav, Gautham Parameshwar Hegde
  • Patent number: 11461043
    Abstract: A storage device set includes a storage device configured to communicate with a host, the storage device including a controller configured to generate encrypted input data by encrypting data; and a reconfigurable logic chip configured to receive the encrypted input data from the storage device, generate processed data by processing the encrypted input data according to a configuration, and generate encrypted output data by encrypting the processed data.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-geun Park, Phil-yong Jung, Ho-jun Shim, Sang-young Ye
  • Patent number: 11461031
    Abstract: A migration replication relationship for data migration between a migration-source volume on a first storage controller and a migration-target volume on a second storage controller, a volume represents a virtualized device. The method presents the migration-source volume and the migration-target volume as a same volume to a host whilst using differentiated target port descriptors to define different discoverable paths to the each. During data migration, the method allows input/output operations to the migration-source volume by presenting target ports of the first storage controller in an available state and deters input/output operations to the migration-target volume by presenting target ports on the second storage controller in a standby state whilst allowing host discovery of paths to the migration-target volume.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: October 4, 2022
    Assignee: International Business Machines Corporation
    Inventors: Timothy Andrew Moran, Christopher Bulmer, Christopher Canto, Warren Hawkins
  • Patent number: 11455268
    Abstract: The present disclosure relates generally to electronic interconnects including one or more switches and, more particularly, to delay bound determination for electronic interconnects.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 27, 2022
    Assignee: Arm Limited
    Inventors: Matteo Maria Andreozzi, Michael Andrew Campbell, Giovanni Stea, Raffaele Zippo
  • Patent number: 11411880
    Abstract: Provided are a connection management mechanism and a connection management method with which computer bus connections can be managed such that failures and freezes do not occur in a computer system when delays and packet losses occur. A connection management unit, which is used in computer bus communication in which packets are transmitted between a request source and a request destination, has a dummy return packet generation/transmission function wherein a dummy return packet is generated and is transmitted to the request source when a delay or loss occurs in a return packet transmitted from the request destination, and/or a filter function wherein, after transmission of the dummy return packet, a legitimate return packet arriving from the request destination is discarded.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 9, 2022
    Assignee: NEC CORPORATION
    Inventors: Yuki Hayashi, Jun Suzuki, Masaki Kan
  • Patent number: 11392318
    Abstract: The various embodiments disclose an electronic device including: a storage including a non-volatile memory having a buffer space and a storage space, a storage device controller, and a storage interface, and a processor. According to various embodiments, the processor may be configured to perform control to determine whether the storage supports a high speed data storage mode using a buffer space of a non-volatile memory of the storage, activate a function of writing data buffered in the buffer space of the non-volatile memory into a storage space of the non-volatile memory based on the storage interface operating in a first state based on the storage supporting the high speed data storage mode, and transition the storage interface of the storage to the first state based on no request to the storage being generated during a predetermined time period based on the storage interface operating in a second state.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wonsuk Jung, Junwoo Lee, Jintae Jang
  • Patent number: 11385834
    Abstract: A data storage device and a storage system including the same are disclosed. The data storage device includes a nonvolatile memory device configured to store user data and metadata including data type identification information matched with the user data, and a controller to control the nonvolatile memory device to be switched to a cold data storage device for storing cold data only when a number of program-erase (PE) cycles of the nonvolatile memory device is equal to or larger than a reference value.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventors: Yong Jin, Jun Hee Ryu, Jong Chan Kim, Kyong Seon Lim
  • Patent number: 11379141
    Abstract: A method of operating a Solid State Drive (SSD), comprising identifying critical metadata corresponding to data previously written to the SSD. In response to a power loss event the method also includes storing the critical metadata in a non-volatile memory. Further, the method also involves writing a first table of contents corresponding to the stored critical metadata to the non-volatile memory and storing a pointer to the first table of contents. A Solid State Drive (SSD) including a memory controller, a non-volatile memory, and a power loss protection capacitor. The memory controller is configured to identify critical metadata corresponding to data previously written to the SSD. The memory controller is also configured to, in response to a power loss event, store the critical metadata in a non-volatile memory write a first table of contents corresponding to the stored critical metadata to the non-volatile memory, and store a pointer to the first table of contents.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: July 5, 2022
    Assignee: Kioxia Corporation
    Inventor: Amit Jain
  • Patent number: 11379373
    Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Anirban Ray, Paul Stonelake, Samir Mittal, Gurpreet Anand
  • Patent number: 11372564
    Abstract: A data processing system includes a plurality of resources suitable for processing data, a host suitable for requesting at least one of the plurality of resources to process the data, a plurality of data paths suitable for transferring the data between the host and the plurality of resources, and an arbiter suitable for dividing the plurality of resources into a plurality of groups, allocating at least one first data path of the plurality of data paths to each of the groups, and rearranging the plurality of groups, based on their respective transmission statuses, by additionally allocating at least one second data path of the plurality of data paths to each of the groups or by moving at least one resource from one of the plurality of groups to another of the plurality of groups.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventor: Kyung-Soo Lee
  • Patent number: 11372763
    Abstract: Various embodiments described herein provide for using a prefetch buffer for a data interface bridge, which can be used with a memory sub-system to increase read access or sequential read access of data from a memory device coupled to the data interface bridge.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Ashay Narsale, Robert Walker
  • Patent number: 11372785
    Abstract: A server system is provided that includes one or more compute nodes that include at least one processor and a host memory device. The server system further includes a plurality of solid-state drive (SSD) devices, a local non-volatile memory express virtualization (LNV) device, and a non-transparent (NT) switch for a peripheral component interconnect express (PCIe) bus that interconnects the plurality of SSD devices and the LNV device to the at least one processor of each compute node. The LNV device is configured to virtualize hardware resources of the plurality of SSD devices. The plurality of SSD devices are configured to directly access data buffers of the host memory device. The NT switch is configured to hide the plurality of SSD devices such that the plurality of SSD devices are not visible to the at least one processor of each compute node.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: June 28, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vadim Makhervaks, Aaron William Ogus, Jason David Adrian
  • Patent number: 11366755
    Abstract: The controller that controls the industrial machine comprises a storage area that stores an operation program, a cache memory, a cache control unit, and an analysis unit, the analysis unit pre-reads a command subsequent to a command included in the operation program loaded in the cache memory, in a case where it is determined that an operation load on a CPU in a command included in the operation program is below a prescribed value, adds, to the command, a cache control command for loading of a subprogram into the cache memory in accordance with a predetermined condition, in a case where a subprogram call command is confirmed present, and makes a cache control request to the cache control unit, responsive to the added cache control command, and the cache control unit loads the subprogram in the cache memory, based on the cache control request.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: June 21, 2022
    Assignee: FANUC CORPORATION
    Inventors: Kazuyuki Mikami, Hideo Ogino, Takenori Ono, Manabu Saitou