Patents Examined by Erik Kielin
  • Patent number: 10833144
    Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: November 10, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Teck-Chong Lee
  • Patent number: 10833112
    Abstract: An image sensor includes a first transfer gate formed over a substrate, and including a first projection; a second transfer gate formed over the substrate, neighboring the first transfer gate, and including a second projection; and a floating diffusion formed in the substrate, and partially overlapping with the first transfer gate and the second transfer gate, wherein the first projection and the second projection face each other.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 10, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung-Kun Park, Hye-Won Mun
  • Patent number: 10811638
    Abstract: A display device includes a display panel having a display surface, and a polarizing unit on the display surface of the display panel, the polarizing unit including a linear polarizer that includes at least two portions having different transmittances from each other.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: October 20, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Haegoo Jung, Jangseok Ma, Dohyung Ryu, Jaewoo Song, Jaehoon Lee
  • Patent number: 10804313
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
  • Patent number: 10797226
    Abstract: A magnetoresistive memory cell is provided including a substrate. An inter-layer dielectric layer is disposed on the substrate. A via structure is disposed in the inter-layer dielectric layer. A magnetic pinned layer is disposed on the via structure. A tunnel barrier layer is disposed on the magnetic pinned layer to cover a top and a sidewall of the magnetic pinned layer, wherein the tunnel barrier layer comprises a horizontal extending portion outward from a bottom of the sidewall. A magnetic free layer with a -like structure is disposed on the tunnel barrier layer, wherein the magnetic free layer is isolated from the magnetic pinned layer by the tunnel bather layer. A spacer is disposed on the sidewall of the magnetic free layer. The spacer extends to the inter-layer dielectric layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Sheng Feng, Yu-Chun Chen, Chiu-Jung Chiu, Hung-Chan Lin
  • Patent number: 10784203
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 10777510
    Abstract: A semiconductor device and a method of manufacture thereof are provided. The method for manufacturing the semiconductor device includes forming a first dielectric layer on a substrate. Next, forming a first dummy metal layer on the first dielectric layer. Then, forming a second dielectric layer over the first dummy metal layer. Furthermore, forming an opening in the second dielectric layer and the first dummy metal layer. Then, forming a dummy via in the opening, wherein the dummy via extending through the second dielectric layer and at least partially through the first dummy metal layer. Finally, forming a second dummy metal layer on the second dielectric layer and contact the dummy via.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 10763323
    Abstract: An organic light-emitting diode display may have rounded corners. A negative power supply path may be used to distribute a negative voltage to a cathode layer, while a positive power supply path may be used to distribute a positive power supply voltage to each pixel in the display. The positive power supply path may have a cutout that is occupied by the negative power supply path to decrease resistance of the negative power supply path in a rounded corner of the display. To mitigate reflections caused by the positive power supply path being formed over tightly spaced data lines, the positive power supply path may be omitted in a rounded corner of the display, a shielding layer may be formed over the positive power supply path in the rounded corner, or non-linear gate lines may be formed over the positive power supply path.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: September 1, 2020
    Assignee: Apple Inc.
    Inventors: Tiffany T. Moy, Yuchi Che, Seonpil Jang, Warren S. Rieutort-Louis, Bhadrinarayana Lalgudi Visweswaran, Jae Won Choi, Abbas Jamshidi Roudbari, Myung-Kwan Ryu, Hirokazu Yamagata, Keisuke Otsu
  • Patent number: 10763258
    Abstract: An integrated circuit includes a substrate, at least one n-type semiconductor device, and at least one p-type semiconductor device. The n-type semiconductor device is present on the substrate. The n-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the n-type semiconductor device and the sidewall of the gate structure of the n-type semiconductor device intersect to form an interior angle. The p-type semiconductor device is present on the substrate. The p-type semiconductor device includes a gate structure having a bottom surface and at least one sidewall. The bottom surface of the gate structure of the p-type semiconductor device and the sidewall of the gate structure of the p-type semiconductor device intersect to form an interior angle smaller than the interior angle of the gate structure of the n-type semiconductor device.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10748948
    Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Chu, Yeur-Luen Tu, Cheng-Yuan Tsai
  • Patent number: 10727070
    Abstract: A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10714577
    Abstract: Structures for a field-effect transistor and methods for fabricating a structure for a field-effect transistor. First and second device structure are respectively formed in first and second device regions, and a first dielectric layer is formed over the first and second device regions. The first dielectric layer includes a recess defining a step at a transition between the first and second device regions, and a second dielectric layer is arranged within the recess in the first dielectric layer. A third dielectric layer is arranged over the first dielectric layer in the first device region and over the second dielectric layer in the second device region. A contact, which is coupled with the second device structure, extends through the first, second, and third dielectric layers in the second device region.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hong, Hui Zang, Hsien-Ching Lo
  • Patent number: 10707208
    Abstract: A method of forming vertical fins on a substrate at the same time, the method including, forming a mask segment on a first region of the substrate while exposing the surface of a second region of the substrate, removing a portion of the substrate in the second region to form a recess, forming a fin layer in the recess, where the fin layer has a different material composition than the substrate, and forming at least one vertical fin on the first region of the substrate and at least one vertical fin on the second region of the substrate, where the vertical fin on the second region of the substrate includes a fin layer pillar formed from the fin layer and a substrate pillar.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10700118
    Abstract: A multispectral imaging device comprises a first photoelectric conversion module and a second photoelectric conversion module. The first photoelectric conversion module further includes a first photoelectric conversion layer located between a first conducting layer and a second conducting layer. The first conducting layer, coupled to a first constant potential, is configured to allow visible light and infrared light to pass through. The first photoelectric conversion layer is configured to convert the visible light into a first electrical signal. The second photoelectric conversion module, formed on a silicon substrate, is configured to receive the infrared light coming from the first photoelectric conversion module.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 30, 2020
    Inventor: Zhongshou Huang
  • Patent number: 10686147
    Abstract: A method for manufacturing an organic light emitting display device includes forming a substrate insulating film an upper surface, a lower surface, and at least one of two side surfaces of a substrate and forming an organic light emitting diode (OLED) on the substrate on which the substrate insulating film is formed. An organic light emitting display device includes a substrate having a first surface, a second surface opposite to the first surface, and side surfaces that extend between the first surface and the second surface, a substrate insulating film disposed on the first surface, the second surface, and at least one of the side surfaces of the substrate, and an OLED disposed on one of the first surface or the second surface of the substrate including the substrate insulating film.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 16, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Sungwoo Choi, Chulho Kim, Yunho Kook, Kyuhwang Lee, Hwankeon Lee
  • Patent number: 10677968
    Abstract: A display device, a method for manufacturing the same, and a head mounted display including the same are disclosed, in which mixing of colors may be avoided. The display device comprises a black matrix covering an edge of a first color filter and a second color filter an edge of the black matrix.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 9, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: JongSung Kim, ChoongKeun Yoo
  • Patent number: 10680164
    Abstract: A Hall effect sensor comprises a semiconductor substrate, a first well formed in the semiconductor substrate, a first ohmic contact formed in the first well, a second ohmic contact formed in the first well, a first terminal electrically coupled to the first ohmic contact, a second terminal electrically coupled to the second ohmic contact, and a first metal layer formed over the semiconductor substrate. The first metal layer comprises a first interconnect and a first trace, where the first trace is formed over the first well, and where the first interconnect electrically couples a first part of the first well to a second part of the first well. The first and second ohmic contacts are each positioned between the first part and the second part of the first well, where the first interconnect is electrically isolated from the first trace.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Ryan Green, Dok Won Lee
  • Patent number: 10658177
    Abstract: In example implementations of a heterogeneous substrate, the heterogeneous substrate includes a first material having an air trench, a second material coupled to the first material, a dielectric mask on a first portion of the second material and an active region that is grown on a remaining portion of the second material. An air gap may be formed in the air trench by the second material coupled to the first material. Defects in the second material may be contained to an area below the dielectric mask and the active region may remain defect free.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 19, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Di Liang
  • Patent number: 10644091
    Abstract: An electronic device, a display panel, and a method for manufacturing the display panel are provided. The display panel includes a substrate, and data fan-out lines and a power supply fan-out line arranged in a step region of the substrate. An orthographic projection of an overlapping region between the power supply fan-out line and the encapsulating region on the substrate is non-overlapping with an orthographic projection of an overlapping region between each of the data fan-out lines and the encapsulating region on the substrate, thereby reducing the encapsulating failure of the sealant due to a common overlapping region of the data fan-out lines and the power supply fan-out line in the encapsulating region, and improving the reliability of the display panel.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 5, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Xinzhao Liu, Kaihong Huang
  • Patent number: 10643990
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Donald R. Disney, Jongjib Kim, Wen-Cheng Lin