Patents Examined by Erik Kielin
  • Patent number: 11562925
    Abstract: Embodiments disclosed herein generally relate to methods of depositing a plurality of layers. A doped copper seed layer is deposited in a plurality of feature definitions in a device structure. A first copper seed layer is deposited and then the first copper seed layer is doped to form a doped copper seed layer, or a doped copper seed layer is deposited directly. The doped copper seed layer leads to increased flowability, reducing poor step coverage, overhang, and voids in the copper layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 24, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shirish Pethe, Fuhong Zhang, Joung Joo Lee, Rui Li, Xiangjin Xie, Xianmin Tang
  • Patent number: 11562986
    Abstract: Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jian Li, Steven K. Groothuis
  • Patent number: 11561195
    Abstract: A monolithic, three-dimensional (3D) integrated circuit (IC) device includes a sensing layer, a memory layer, and a processing layer. The sensing layer includes a plurality of carbon nanotube field-effect transistors (CNFETs) that are functionalized with at least 50 functional materials to generate data in response to exposure to a gas. The memory layer stores the data generated by the plurality of CNFETs, and the processing layer identifies one or more components of the gas based on the data generated by the plurality of CNFETs.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: January 24, 2023
    Assignee: Massachusetts Institute of Technology
    Inventors: Max Shulaker, Mindy Deanna Bishop
  • Patent number: 11552082
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 10, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
  • Patent number: 11527594
    Abstract: An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: December 13, 2022
    Inventors: Shin-Hyuk Yang, Kwang-Soo Lee, Doo-Hyun Kim, Jee-Hoon Kim
  • Patent number: 11527420
    Abstract: A release layer is formed on a surface of an integrated circuit wafer. The surface is passivated and includes metal contact materials. A stress-engineered film having an intrinsic stress profile is deposited over the release layer. The stress-engineered film is patterned and the release layer is undercut etched so that a released portion of the patterned stress-engineered film is released from the surface while leaving an anchor portion fixed to the surface. The intrinsic stress profile in the stress-engineered film biases the released portion away from the surface. The released portion is placed entirely within an area defined by the metal contact material.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: December 13, 2022
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Christopher L. Chua, Qian Wang, Eugene M. Chow
  • Patent number: 11515169
    Abstract: A semiconductor manufacturing apparatus includes: a stage installed inside a processing chamber and holding a semiconductor substrate having a high-k insulating film including silicate; and a gas supply line including a first system supplying reactive gas to the processing chamber and a second system supplying catalytic gas to the processing chamber, wherein mixed gas which includes complex forming gas reacting with a metal element included in the high-k insulating film to form a first volatile organometallic complex and complex stabilizing material gas increasing stability of the first organometallic complex is supplied as the reactive gas, and catalytic gas using a second organometallic complex, which modifies the high-k insulating film and promotes a formation reaction of the first organometallic complex, as a raw material is supplied.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: November 29, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventor: Yoshihide Yamaguchi
  • Patent number: 11508573
    Abstract: In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Santanu Sarkar, Jay Steven Brown, Shu Qin, Yongjun Jeff Hu, Farrell Martin Good
  • Patent number: 11502039
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Patent number: 11501974
    Abstract: An electrode structure of a back electrode including metal layers laminated in the following order: a Ti layer, a Ni layer, and a Ag alloy layer. The Ag alloy layer includes an Ag alloy and an addition metal M selected from Sn, Sb, and Pd. The electrode structure is configured such that when subjected to elemental analysis with an X-ray photoelectron spectrometer in the depth direction from the Ag alloy layer to the Ni layer, on the boundary between the Ni layer and the Ag alloy layer, an intermediate region where spectra derived from all the metals, Ni, Ag, and the addition element M, can be detected is observable, and, when each metal content in the intermediate region is converted based on the spectra derived from all the metals Ni, Ag, and the addition element M, the maximum of the addition element M content is 5 at % or more.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 15, 2022
    Assignee: TANAKA KIKINZOKU KOGYO K.K.
    Inventors: Yohei Mizuno, Tetsuya Kato, Chiharu Ishikura
  • Patent number: 11495674
    Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ling Chan, Derek Chen, Liang-Yin Chen, Chien-I Kuo
  • Patent number: 11488837
    Abstract: A method for fabricating a high-voltage (HV) transistor is provided. The method includes providing a substrate, having a first isolation structure and a second isolation structure in the substrate and a recess in the substrate between the first and second isolation structures. Further, a hydrogen annealing process is performed over the recess. A sacrificial dielectric layer is formed on the recess. The sacrificial dielectric layer is removed, wherein a portion of the first and second isolation structures is also removed. A gate oxide layer is formed in the recess between the first and second isolation structures after the hydrogen annealing process.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: November 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Chun Yu Chen, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Patent number: 11488842
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor die and a second semiconductor die to a first substrate, forming a conductive layer over the first semiconductor die, the second semiconductor die, and the first substrate, applying an encapsulant over the conductive layer, and removing a portion of the encapsulant, wherein the removing the portion of the encapsulant exposes the conductive layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Yu Tsai, Tsung-Shang Wei, Yu-Sheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 11488820
    Abstract: A method of fabricating layered structure is disclosed. A basal layer is formed. A laminate is formed on the basal layer, and the laminate includes a device layer, a sacrificial layer and a protection layer stacked in sequence. The device layer, the sacrificial layer and the protection layer are etched to obtain a patterned laminate. A first dielectric layer covering a lateral surface of the patterned laminate is formed. Part of the first dielectric layer and part of the protection layer are removed by polishing. The protection layer of the patterned laminate is etched to expose the sacrificial layer. A through hole in the first dielectric layer is formed to expose the basal layer. The sacrificial layer of the patterned laminate is etched to form an opening in the first dielectric layer, and the opening exposes a top surface of the device layer.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: November 1, 2022
    Assignee: JIANGSU ADVANCED MEMORY TECHNOLOGY CO., LTD.
    Inventors: Chung Hon Lam, Hao Ren Zhuang, Kuo-Feng Lo, Yen Yu Hsu
  • Patent number: 11482597
    Abstract: A semiconductor wafer of monocrystalline silicon. The semiconductor wafer having: a substrate wafer of monocrystalline silicon; and a layer of monocrystalline silicon that lies on a front side of the substrate wafer. The substrate wafer has a crystal orientation. An averaged front side-based ZDD of the semiconductor wafer, with a division of a surface of an epitaxial layer into 16 sectors and an edge exclusion of 1 mm, is not less than ?30 nm/mm2 and not more than 0 nm/mm2. An ESFQRmax of the semiconductor wafer, with an edge exclusion of 1 mm and 72 sectors each with a length of 30 mm, is at most 10 nm.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 25, 2022
    Assignee: SILTRONIC AG
    Inventors: Norbert Werner, Christian Hager
  • Patent number: 11474069
    Abstract: Disclosed is an open-junction ionic transistor which includes: a substrate; a p type gel which is formed as a polyelectrolyte gel on the substrate; an n type gel which is formed as the polyelectrolyte gel on the substrate and having one side contacting one side of the p type gel; a first reservoir contacting the other side of the p type gel; a second reservoir contacting the other side of the n type gel; and an encapsulation layer covering the p type gel, the n type gel, the first reservoir, and the second reservoir, in which on the encapsulation layer, an injection unit for injecting an ion input is formed at a location corresponding to an interface contacting the p type gel and the n type gel and when reverse bias voltage is applied between the p type gel and the n type gel, the ion input injected through the injection unit is amplified and ionic current peak is generated.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: October 18, 2022
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jeong-Yun Sun, Young-Chang Joo, Taek Dong Chung, Hae-Ryung Lee, Seung-Min Lim, Seok Hee Han, Hyunjae Yoo
  • Patent number: 11469185
    Abstract: Semiconductor packages having support members are provided. Support members can mitigate damage to a semiconductor die mounted on a semiconductor package. In some embodiments, an arrangement of support packages can be formed at respective locations of a frame layer that serves as a stiffener for the semiconductor package. Each support member in the arrangement can be formed from a same material of the frame layer or a different material. In some embodiments, a support member can be mounted or otherwise coupled to an exposed surface of the frame layer. In addition or in other embodiments, a support member can be mounted on a surface that supports the semiconductor die. The arrangement of support members can include support members comprising a first material and/or other support members formed from respective materials. A support member can be formed from a metal, a metal alloy, a semiconductor, a polymer, a composite material, or a porous material.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 11, 2022
    Assignee: Intel Corporation
    Inventors: Je-Young Chang, Shubhada H. Sahasrabudhe, Tannaz Harirchian
  • Patent number: 11462687
    Abstract: The embodiments of the present disclosure provide a method of fabricating a display backplate. The method of fabricating the display backplate may include forming a channel layer on a surface of a substrate. The channel layer may include a liquid storage portion, a plurality of pixel channels, and a plurality of moving electrodes. Each of the plurality of pixel channels may include a plurality of sub-pixel grooves. The method of fabricating the display backplate may further include printing ink droplets into the liquid storage portion and moving the ink droplets into the plurality of sub-pixel grooves by applying a moving voltage to the moving electrodes.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 4, 2022
    Assignee: BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD.
    Inventors: Dejiang Zhao, Guangcai Yuan
  • Patent number: 11462625
    Abstract: The semiconductor device includes a well region disposed in a surface layer of a semiconductor substrate, a source region and a drain region arranged separated from each other in a surface layer of the well region, a channel region disposed between the source region and the drain region, and a gate electrode disposed on the channel region via a gate insulating film containing fluorine, in which concentration of fluorine existing in a first interface, the first interface being an interface of the gate insulating film with the gate electrode, and concentration of fluorine existing in a second interface, the second interface being an interface of the gate insulating film with the channel region, are higher than concentration of fluorine existing in a middle region in the depth direction of the gate insulating film, and fluorine concentration in the first interface is higher than fluorine concentration in the second interface.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: October 4, 2022
    Assignee: Asahi Kasel Microdevices Corporation
    Inventor: Shuntaro Fujii
  • Patent number: 11456185
    Abstract: In certain embodiments, a method for processing a substrate includes applying a surface treatment to selected surfaces of the substrate. The substrate has a non-planar topography including structures defining recesses. The method further includes depositing a fill material on the substrate by spin-on deposition. The surface treatment directs the fill material to the recesses and away from the selected surfaces to fill the recesses with the fill material without adhering to the selected surfaces. The method further includes removing the surface treatment from the selected surfaces of the substrate and depositing a planarizing film on the substrate by spin-on deposition. The planarizing film is deposited on the selected surfaces and top surfaces of the fill material.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: September 27, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Ryan Burns, Mark Somervell, Corey Lemley