Patents Examined by Erik Kielin
  • Patent number: 10677968
    Abstract: A display device, a method for manufacturing the same, and a head mounted display including the same are disclosed, in which mixing of colors may be avoided. The display device comprises a black matrix covering an edge of a first color filter and a second color filter an edge of the black matrix.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 9, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: JongSung Kim, ChoongKeun Yoo
  • Patent number: 10680164
    Abstract: A Hall effect sensor comprises a semiconductor substrate, a first well formed in the semiconductor substrate, a first ohmic contact formed in the first well, a second ohmic contact formed in the first well, a first terminal electrically coupled to the first ohmic contact, a second terminal electrically coupled to the second ohmic contact, and a first metal layer formed over the semiconductor substrate. The first metal layer comprises a first interconnect and a first trace, where the first trace is formed over the first well, and where the first interconnect electrically couples a first part of the first well to a second part of the first well. The first and second ohmic contacts are each positioned between the first part and the second part of the first well, where the first interconnect is electrically isolated from the first trace.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 9, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Keith Ryan Green, Dok Won Lee
  • Patent number: 10658177
    Abstract: In example implementations of a heterogeneous substrate, the heterogeneous substrate includes a first material having an air trench, a second material coupled to the first material, a dielectric mask on a first portion of the second material and an active region that is grown on a remaining portion of the second material. An air gap may be formed in the air trench by the second material coupled to the first material. Defects in the second material may be contained to an area below the dielectric mask and the active region may remain defect free.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 19, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Di Liang
  • Patent number: 10644091
    Abstract: An electronic device, a display panel, and a method for manufacturing the display panel are provided. The display panel includes a substrate, and data fan-out lines and a power supply fan-out line arranged in a step region of the substrate. An orthographic projection of an overlapping region between the power supply fan-out line and the encapsulating region on the substrate is non-overlapping with an orthographic projection of an overlapping region between each of the data fan-out lines and the encapsulating region on the substrate, thereby reducing the encapsulating failure of the sealant due to a common overlapping region of the data fan-out lines and the power supply fan-out line in the encapsulating region, and improving the reliability of the display panel.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: May 5, 2020
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Xinzhao Liu, Kaihong Huang
  • Patent number: 10643990
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an ultra-high voltage resistor and methods of manufacture. The structure includes at least one resistor coupled to a well of a doped substrate, the at least one resistor being separated vertically from the well by an isolation region with one end of the resistor being attached to an input pad and another end coupled to circuitry.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Donald R. Disney, Jongjib Kim, Wen-Cheng Lin
  • Patent number: 10593634
    Abstract: Various embodiments of an integrated device package with integrated antennas are disclosed. In some embodiments, an antenna can be defined along a die pad of the package. In some embodiments, an antenna can be disposed in a first packaging component, and an integrated device die can be disposed in a second packaging component. The first and second packaging components can be stacked on one another and electrically connected. In some embodiments, a package can include one or a plurality of antennas disposed along a wall of a package body. The plurality of antennas can be disposed facing different directions from the package.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 17, 2020
    Assignee: Analog Devices, Inc.
    Inventors: Youn-Jae Kook, Yeonsung Kim, Dipak Sengupta
  • Patent number: 10580702
    Abstract: A semiconductor device includes first active patterns and second active patterns on a substrate, a first source/drain region on the first active patterns, a second source/drain region on the second active patterns and a device isolation layer filling a first trench between adjacent ones of the first active patterns and a second trench between adjacent ones of the second active patterns. A liner layer is disposed on the device isolation layer between the adjacent ones of the second active patterns. The device isolation layer between the adjacent ones of the first active patterns has a recess therein under the first source/drain region and a bottom surface of the liner layer between the adjacent ones of the second active patterns is higher than the recess.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunki Min, Donghyun Roh
  • Patent number: 10563014
    Abstract: This disclosure relates to dielectric film forming composition containing at least one fully imidized polyimide polymer; at least one inorganic filler; at least one metal-containing (meth)acrylate compound; and at least one catalyst. The dielectric film formed by such a composition can have a relatively low coefficient of thermal expansion (CTE) and a relatively high optical transparency.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: February 18, 2020
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Sanjay Malik, William A. Reinerth, Binod B. De
  • Patent number: 10559615
    Abstract: A method for manufacturing a high-dynamic-range color image sensor includes (a) depositing a color filter layer on a silicon substrate having a photosensitive pixel array with a plurality of first pixels and a plurality of second pixels, to form (i) a plurality of first color filters above a first subset of each of the plurality of first pixels and the plurality of second pixels and (ii) a plurality of second color filters above a second subset of each of the plurality of first pixels and the plurality of second pixels, wherein thickness of the second color filters exceeds thickness of the first color filters, and (b) depositing, on the color filter layer, a dynamic-range extending layer including grey filters above the second pixels to attenuate light propagating toward the second pixels, combined thickness of the color filter layer and the dynamic-range extending layer being uniform across the photosensitive pixel array.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 11, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chen-Wei Lu, Dajiang Yang, Oray Orkun Cellek, Duli Mao
  • Patent number: 10559664
    Abstract: A method of manufacturing a semiconductor device includes assigning a plurality of chip regions on an epitaxial-growth layer of a semiconductor substrate where the epitaxial-growth layer is grown on a bulk layer and forming a plurality of device structures on the plurality of chip regions, respectively, thinning the semiconductor substrate from a bottom-surface side of the bulk layer, bonding a supporting-substrate on a bottom surface of the thinned semiconductor substrate, selectively removing the supporting-substrate so that the bottom surface of the semiconductor substrate is exposed, at locations corresponding to positions of each of main current paths in the plurality of device structures, respectively, dicing the semiconductor substrate together with the supporting-substrate along dicing lanes between the plurality of the chip regions so as to form a plurality of chips.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa
  • Patent number: 10553832
    Abstract: According to a lighting apparatus of the present disclosure, an organic light emitting material and a metal layer may be deposited in a state that an edge region of a film being transported is blocked by a shielding member not to form an organic light emitting layer and a second electrode in a region on which a pad is formed. A lighting apparatus may be completed by separating the film as it is cut in a width direction, wherein the organic light emitting layer and the second electrode are exposed to the outside through the cut surface, and an open region from which the organic light emitting layer and the second electrode are removed in parallel to both cut surfaces may be formed within the lighting apparatus spaced apart from the cut surface of the film to disconnect the organic light emitting layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 4, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Taejoon Song, Namkook Kim, Shinbok Lee, Soonsung Yoo, Hwankeon Lee
  • Patent number: 10553601
    Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: February 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsutomu Tezuka, Fumitaka Arai, Keiji Ikeda, Tomomasa Ueda, Nobuyoshi Saito, Chika Tanaka, Kentaro Miura, Tomoaki Sawabe
  • Patent number: 10535698
    Abstract: The present disclosure relates to an image sensor with a pad structure formed during a front-end-of-line process. The pad structure can be formed prior to formation of back side deep trench isolation structures and metal grid structures. An opening is formed on a back side of the image sensor device to expose the embedded pad structure and to form electrical connections.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Yin-Chieh Huang
  • Patent number: 10535822
    Abstract: The present invention relates to new semiconducting compounds having at least one optionally substituted benzo[d][1,2,3]thiadiazole moiety. The compounds disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions.
    Type: Grant
    Filed: February 12, 2017
    Date of Patent: January 14, 2020
    Assignee: Flexterra, Inc.
    Inventors: Antonio Facchetti, Zhihua Chen, Jennifer E. Brown
  • Patent number: 10529650
    Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 10529764
    Abstract: The present disclosure relates to a semiconductor device, a solid state imaging element, and an electronic apparatus in which the adverse effect due to hot carrier luminescence can be suppressed. In them, an element formation unit in which a plurality of elements are formed and an interconnection unit in which interconnections connecting elements are formed are stacked. A structure object formed between a light receiving element that receives light and performs photoelectric conversion and an active element that forms a peripheral circuit placed around the light receiving element in such a manner that the gap in the thickness direction of the element formation unit is not more than a prescribed spacing and formed of a material that inhibits the propagation of light is placed in the element formation unit. The present technology can be applied to a back-side illumination solid state imaging element, for example.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 7, 2020
    Assignee: Sony Corporation
    Inventors: Shoji Kobayashi, Shin Iwabuchi, Toshikazu Shibayama, Mamoru Suzuki, Shunsuke Maruyama
  • Patent number: 10529782
    Abstract: In an embodiment, an organic light emitting display device includes a first substrate, a display region, a pad portion, lines, and a moisture-transmission delay layer. The display region includes sub-pixels disposed on the first substrate. The pad portion is disposed on the first substrate and electrically connected to an external device. The lines are disposed between the pad portion and the display region and electrically connected to the external device, and transfer a signal or power to the external device. The moisture-transmission delay layer covers edges of the lines.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: January 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Sangil Shin, Kiyoung Sung, Youngju Park, Sanghyun Lim, SangHoon Jeong
  • Patent number: 10522656
    Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Ling Chan, Derek Chen, Liang-Yin Chen, Chien-I Kuo
  • Patent number: 10522526
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Lin Chung-Yi, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 10515901
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai