Patents Examined by Ernest Unelus
  • Patent number: 11449276
    Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David Hulton, Jeremy Chritz, Tamara Schmitz
  • Patent number: 11449445
    Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 20, 2022
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang
  • Patent number: 11449455
    Abstract: During operation, the system receives, by a master node, a first I/O request with associated data, wherein the master node is in communication with a first plurality of storage drives via a switch based on a network protocol, wherein the master node and the first plurality of storage drives are allowed to reside in different cabinets, and wherein a respective collection of storage drives are coupled to a converter module, which is configured to convert data between the network protocol and an I/O protocol used to access the storage drives. The system identifies, by the master node, a first collection of storage drives from the first plurality on which to execute the first I/O request. The system executes, based on a communication via the switch and a converter module associated with the first collection of storage drives, the first I/O request on the first collection of storage drives.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: September 20, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11442661
    Abstract: A RAID parity data generation offload system includes a RAID storage controller device that determines that a RAID parity data storage device loading for a RAID parity data storage device exceeds a loading threshold, and then generates and transmits a RAID parity data generation offload command associated with a RAID parity data update required in response to a RAID primary data update. A first RAID primary data storage device receives the RAID parity data generation offload command, and then retrieves current parity data from the RAID parity data storage device, and performs an XOR operation using the current parity data, current primary data, and updated primary data associated with the RAID primary data update in order to generate updated parity data. The first RAID primary data storage device then provides the updated parity data for storage on the RAID parity data storage device in place of the current parity data.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: September 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Gary Benedict Kotzur, William Emmett Lynn, Kevin Thomas Marks, Chandrashekar Nelogal, James Peter Giannoules, Austin Patrick Bolen
  • Patent number: 11435947
    Abstract: A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wan-Soo Choi, Young Wook Kim, Dong Eun Shin, Yong Chan Jo
  • Patent number: 11436185
    Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 6, 2022
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Patent number: 11435937
    Abstract: Facilitating monitoring of service processors associated with a data storage system is provided herein. A system can include a monitoring component and an interpretation component. The monitoring component monitors a service processor that controls one or more functions for a data storage system. The monitoring component also generates trend data indicative of trend information for the service processor. The interpretation component performs one or more actions associated with the data storage system in response to a determination that the trend data satisfies a set of defined criteria associated with monitored conditions for the data storage system.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 6, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jeffrey D. Esposito, Michael P. Blanchard
  • Patent number: 11429282
    Abstract: A memory system may include a plurality of memory dies configured to store data therein, and a controller coupled to the plurality of memory dies through a plurality of channels, and configured to correlate at least some of a plurality of read requests and transferring the plurality of read requests to the plurality of channels, such that the plurality of read requests are processed in an interleaving way through the plurality of channels, when controlling the plurality of memory dies for the plurality of read requests. The controller may determine whether to perform the correlation operation in response to the number of the plurality of read requests, wherein the plurality of read requests include a read request for an internal operation of the controller and a read request received from a host.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11422735
    Abstract: Techniques are provided for artificial intelligence-based storage monitoring. In an example, a system determines structured and unstructured attributes of a folder in a file system and provides them to an trained artificial intelligence model that outputs whether the folder is interesting or not. The folders labelled interesting by the trained artificial intelligence model can be further refined to a subset of folders that are placed in a watch list, and monitored for changes.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: August 23, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Min Gong, Michael Marrotte
  • Patent number: 11416733
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, relating to multi-task recurrent neural networks. One of the methods includes maintaining data specifying, for a recurrent neural network, a separate internal state for each of a plurality of memory regions; receiving a current input; identifying a particular memory region of the memory access address defined by the current input; selecting, from the internal states specified in the maintained data, the internal state for the particular memory region; processing, in accordance with the selected internal state for the particular memory region, the current input in the sequence of inputs using the recurrent neural network to: generate an output, the output defining a probability distribution of a predicted memory access address, and update the selected internal state of the particular memory region; and associating the updated selected internal state with the particular memory region in the maintained data.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 16, 2022
    Assignee: Google LLC
    Inventors: Milad Olia Hashemi, Jamie Alexander Smith, Kevin Jordan Swersky
  • Patent number: 11416171
    Abstract: The present disclosure generally relate to dynamically changing predictive latency related attributes to increase the deterministic window (DTWIN) of operation. The host device workload characteristics as well as the memory device's current condition provide valuable information for the duration of the DTWIN. If the memory device is near the end of life, then the DTWIN duration will be smaller. Additionally, if the workload from the host device is heavy, then the DTWIN duration will also be smaller. Rather than utilizing a fixed DTWIN duration based upon worst case scenarios for host device workload and memory device condition, dynamically adjusting the DTWIN duration based upon the workload and condition will provide a DTWIN duration that can gradually decrease over time from a much longer DTWIN duration than is currently available.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: August 16, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Ariel Navon, Alexander Bazarsky, Judah Gamliel Hahn
  • Patent number: 11409466
    Abstract: In one embodiment, a method provides access to a data storage device from a host coupled to the data storage device. The host is running a plurality of virtual functions. The method includes receiving an inbound request to a memory of a storage device controller of the data storage device. The memory of the storage device controller includes a DRAM memory and a non-DRAM memory. Whether the inbound request is a CMB/PMR transaction request is determined. The CMB/PMR transaction request is scheduled. Whether the scheduled CMB/PMR transaction request is allowed is determined. The allowed CMB/PMR transaction request is issued toward the DRAM memory of the storage device controller.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: August 9, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 11403039
    Abstract: A storage control device includes: a memory configured to store program instructions; and processor circuitry configured to execute the program instruction stored in the memory, the program instruction including: executing a drive path information storage processing configured to cause the memory to store, for each virtual drive, priority information indicating priority to be selected as a path to access the respective virtual drive for each storage control device, the each storage control device being configured to control a corresponding storage device; and executing a determination processing configured to determine a responsible storage control device by using information of virtual drives included in the virtual RAID group and priority information stored in the memory, the responsible storage control device being the storage control device to be used to access a virtual redundant array of inexpensive disks (RAID) group.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 2, 2022
    Assignee: Fujitsu Limited
    Inventor: Atsushi Takakura
  • Patent number: 11403249
    Abstract: A circuit for a bus system is provided. The circuit includes: an ascertainment circuit, which is configured to ascertain a first state in which an absolute difference of a voltage between two bus-side terminals is above a threshold value, to ascertain a second state in which the absolute difference of the voltage between the two bus-side terminals is below a threshold value, to ascertain a bit boundary as a function of a number of state transitions between the first and second state, and a suppression circuit, which is configured to connect a suppression circuit between the two bus-side terminals before the bit boundary.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 2, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Arthur Mutter, Steffen Walker
  • Patent number: 11372584
    Abstract: A storage system includes a plurality of storage nodes 4 each having one or more storage devices. The storage node includes a CPU. The CPU is configured to select a priority path to be notified as a usable path to a higher-level apparatus among paths which allows access of a predetermined logical unit to which a storage area of the storage device is provided from the higher-level apparatus. The CPU is configured to send the priority path as a reply to an inquiry about a path to the predetermined logical unit from the higher-level apparatus.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 28, 2022
    Assignee: HITACHI, LTD.
    Inventors: Shinri Inoue, Kouji Iwamitsu, Takao Totsuka
  • Patent number: 11360670
    Abstract: A dynamic temperature compensation trim for use in temperature compensating a memory operation on a memory call of a memory component. The dynamic temperature compensation trim is based on a temperature of the memory component and based on in-service data for the memory operation on the memory cell. A register for the memory operation is modified based on the dynamic temperature compensation trim.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Larry J. Koudele, Bruce A. Liikanen, Steve Kientz
  • Patent number: 11360890
    Abstract: An apparatus including a plurality of page circuits and a common request circuit. The page circuits may each be implemented within a respective memory bank controller of a memory bank set and store an address and determine a page hit status. The common request circuit may be implemented within the memory bank set and store client requests and issue a command corresponding to the client requests in response to the page hit status and an order of storage of the client requests. The page circuits may comprise half a storage depth of the common request circuit. The common request circuit may be shared between each of the memory bank controllers of the memory bank set. The memory bank controllers may control access to a random access memory. The address, the client requests and the page hit status may enable buffering to provide a preview of upcoming client requests.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: June 14, 2022
    Assignee: Ambarella International LP
    Inventors: Manish Singh, Dingxin Jin
  • Patent number: 11327682
    Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: May 10, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David Hulton, Jeremy Chritz
  • Patent number: 11321023
    Abstract: A storage controller is provided. The storage controller includes circuitry configured to utilize a format command to change a storage volume coupled to the storage controller from a first format to a second format and memory configured to store a data structure for first and second format indications for the storage volume. The storage controller determines if a selected band is initialized to the second format, and if the selected band is not initialized to the second format, the storage controller initializes the selected band to the second format and updates the data structure to indicate the selected band is initialized to the second format.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 3, 2022
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Phillip Raymond Colline, Thomas George Wicklund
  • Patent number: 11314668
    Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Kenneth P. Foust, Amit Kumar Srivastava, George Vergis