Abstract: A method to enable a vehicle's embedded USB Host system to connect to multiple mobile devices through a USB Hub, regardless of whether the mobile devices are configured to act as USB Hosts or USB Devices, without USB On the Go (OTG) controllers or additional vehicle wiring, or inhibiting the functionality of any consumer devices connected to the same USB Hub. Preferably, the method is configured to provide that no additional cabling is required, and no hardware changes are required to be made to the HU. The method can be employed between a vehicle's embedded USB Host, USB Hub and at least one consumer accessible USB port. When the consumer device is acting as a USB Host, signals between the consumer device and the vehicle's embedded USB Host are processed through a USB bridge, thereby rendering the consumer device compatible with the vehicle's embedded USB Host.

Abstract: An example electronic device includes a volatile memory to store a virtual memory device. A processor is to generate an operating system boot sequence in the virtual memory device. The processor uses a firmware interface system driver to create a device path comprising a location in the volatile memory containing the virtual memory device. The processor saves computer operating system files in the virtual memory device. The processor loads the operating system boot sequence by processing the computer operating system files from the virtual memory device.

Abstract: A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Abstract: A memory system may include: a nonvolatile memory device; a volatile memory device to which power is suspended in the sleep mode; and a controller configured to temporarily store internal data in the volatile memory device, the internal data being generated during processing of an operation of the nonvolatile memory device. When a sleep command is received by the memory system from a host, the controller may output the internal data stored in the volatile memory device to the host in response to the sleep command, and then may transfer an acknowledgement for an entry into the sleep mode to the host and enter the sleep mode.

Abstract: A device includes a processor, an SBI, and a plurality of interfaces. The processor is configured to manage operations of the device. The SBI is coupled to the processor. The plurality of interfaces is associated with the SBI. The interfaces of the plurality of interfaces have different interface protocol from one another. The SBI is configured by the processor and the configuration of the SBI activates one interface of the plurality of interfaces at any given time. The active interface that is selected from the plurality of interfaces and a host have a same interface protocol. The active interface is configured to receive host data from the host. The SBI is configured to generate a flag for the processor in response to the active interface receiving the host data. The SBI is configured to transmit device data to the host.

Abstract: A method for use in a storage system, the method comprising: receiving an I/O command; identifying a latency of a first storage device that is associated with the I/O command; and executing the I/O command at least in part based on the latency, wherein executing the I/O command based on the latency includes: performing a first action when the latency is less than a first threshold, and performing a second action when the latency is greater than the first threshold, wherein identifying the latency includes retrieving the latency from a latency database, and wherein the first storage device is part of a storage array, the storage array including one or more second storage devices in addition to the first storage device.

Abstract: A multi-die system includes a non-volatile memory, a first die having a first operational clock, a second die having a second operational clock, and an arbiter. The first die includes a first bus, a first bus filter coupled to the first bus and the arbiter for controlling access signals, a first access controller coupled to the first bus filter, and a first input/output (I/O) filter coupled to the first access controller, the arbiter and the non-volatile memory for controlling access to the non-volatile memory. The second die includes a second bus, a second bus filter coupled to the second bus and the arbiter, a second access controller coupled to the second bus filter, and a second I/O filter coupled to the second access controller, the arbiter and the non-volatile memory. The first and second operational clocks are independent.

Abstract: In a storage system that implements RAID (D+P) with an existing cluster of drives in which the drives have (D+P) partitions that are protection group members, cluster member transfer code creates a new drive cluster when fewer than D+P new drives are added to the storage system. The cluster member transfer code moves one or more drives from the existing cluster into a new cluster so that the number of new drives plus the number of moved drives equals D+P. One or more protection groups may be moved to the new cluster.

Abstract: An electronic device may comprise: a first memory for storing first data at a designated rate; a first processor connected to the first memory and configured to divide the first data into multiple second data, each having a size smaller than the size of the first data; a second memory for storing at least some of the multiple second data at a rate faster than the designated rate; a second processor connected to the second memory and configured to process the at least some of the multiple second data; and a DMA control module, connected to the second processor, for transmitting/receiving data between the first memory and the second memory, wherein the DMA control module is configured to: at least on the basis of a processing command for the multiple second data which is transmitted from the first processor to the second processor, receive, from the first memory, the at least some of the multiple small-sized second data divided from the first data; transmit the at least some of the multiple second data to the s

Abstract: The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

Abstract: An apparatus comprises a set-associative cache comprising a plurality of sets of cache entries, and cache replacement policy storage circuitry to store a plurality of local replacement policy entries. Each local replacement policy entry comprises local replacement policy information specific to a corresponding set of the set-associative cache. Cache control circuitry controls replacement of cache entries of the set-associative cache based on the local replacement policy information stored in the cache replacement policy storage circuitry. The cache replacement policy storage circuitry stores local replacement policy entries for a proper subset of sets of the set-associative cache.

Abstract: The disclosure prevents inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memory device (100) of the disclosure includes a master side memory chip (200) and at least one slave side memory chip (300). A controller (230) of the master side memory chip (200) selects the master side memory chip or the slave side memory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of the master side memory chip is set in a register. The controller (230) controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.

Abstract: There is disclosed a technique for use in managing data storage in a data storage system. A first metric indicative of a specified wear rate for a flash drive is determined where the flash drive has a first portion allocated as logical space and a second portion allocated as over-provisioning space. An allocation ratio indicative of the ratio between the first portion and the second portion is determined. The allocation ration is dynamically adjusted to cause the current wear rate to change.

Abstract: Methods and apparatus for managing power in data storage devices implementing non-volatile memory (NVM) sets are provided. One such apparatus includes a NVM including a first NVM set and a second NVM set, first backend logic circuitry configured to manage data storage in the first NVM set, second backend logic circuitry configured to manage data storage in the second NVM set, and power management circuitry configured to initialize the first and second backend logic circuitry to a high power state, detect an idle state for the first NVM set, store operational settings for the first backend logic circuitry, and transition the first backend logic circuitry to a low power state that consumes less power than the high power state. When a new command arrives, the first backend logic circuitry can be returned to the high power state to handle the command.

Abstract: Described is a system for reclaiming unused storage space when distributing backup data to storage performance-based tiers within a clustered storage environment. The clustered storage environment may organize nodes into storage performance tiers, and each node within a tier may be tuned for a particular type of workload. Accordingly, the system implements a file system that provides the ability to reclaim unused storage space (e.g. perform garbage collection) for specific nodes or tiers independently despite implementing a global namespace. The global namespace may group (or co-locate) aspects of file information with the backup files. For example, file information may be stored on the same node that stores the associated backup files. Accordingly, the system may reclaim unused storage space for each node, or set of nodes forming a storage performance tier, independently and efficiently.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may be configured to control a memory device and include: a request counter configured to generate a count value by counting the number of requests received from a host, and calculate, when the count value matches a preset reference value, an arrival period that is a period between a point in time at which the count value is generated and a point in time at which the count value matches the reference value; a power mode setting component configured to determine an optimal power mode corresponding to the memory device and the memory controller based on the arrival period; and a command controller configured to determine, based on the optimal power mode, points in time at which commands for performing operations corresponding to the respective requests are output.

Abstract: A containerized stream microservice is described. The containerized stream microservice is configured to provide the functionality of volume presentation along with all related interactions including the receipt and processing of IO requests and related services. The containerized stream microservice preferably implements stream metadata in the management of storage operations, and interacts with a store to provide underlying data storage. The store, which may also be referred to as a data store, is where underlying data is stored in a persistent manner. In one example, the store is an object store.

Abstract: An information processing apparatus includes a first memory configured to store first conversion information used for converting a virtual address to a physical address of a memory region to access data stored in the memory region; a second memory configured to store second conversion information used for converting a virtual address to a logical block address of a storage device to access data stored in the storage device; memory management circuitry configured to execute a first processor a second process, according to an access destination of a first virtual address, the first process includes address conversion on the first virtual address using the first conversion information or the second conversion information and memory access to the memory region based on a result of the address conversion, the second process including notification of a first logical block address associated with the first virtual address to an operating system.

Abstract: A method includes receiving, by a storage device and from a host device, a set of protocol parameters initialized by the host device. The set of protocol parameters are used to facilitate data transfer between the host device and the storage device. The method also includes determining that a threshold value associated with the data transfer between the host device and the storage device has been satisfied. The method further includes, in response to determining that the threshold value has been satisfied, sending, by the storage device and to the host device, the set of protocol parameters that were received from the host device.

Abstract: Embodiments of the inventive concept include solid state drive (SSD) multi-card adapters that can include multiple solid state drive cards, which can be incorporated into existing enterprise servers without major architectural changes, thereby enabling the server industry ecosystem to easily integrate evolving solid state drive technologies into servers. The SSD multi-card adapters can include an interface section between various solid state drive cards and drive connector types. The interface section can perform protocol translation, packet switching and routing, data encryption, data compression, management information aggregation, virtualization, and other functions.