Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

Abstract: A method of producing a laser chip includes providing a semiconductor wafer; creating a plurality of depressions arranged one behind another along a breaking direction on a top side of the semiconductor wafer, wherein 1) each depression includes a front boundary face and a rear boundary face successively in the breaking direction, 2) in at least one depression, the rear boundary face is inclined by an angle of 95° to 170° relative to the top side of the semiconductor wafer, 3) at least one depression includes a shoulder adjacent to the rear boundary face, and 4) the shoulder includes a shoulder face parallel to the top side of the semiconductor wafer and adjacent to the rear boundary face; and breaking the semiconductor wafer in the breaking direction at a breaking plane oriented perpendicularly to the top side of the semiconductor wafer and which runs through the depressions.

Abstract: Input/output pins for a chip-embedded substrate may be fabricated by applying a contact-distinct volume of solder to at least two contacts that are recessed within the chip-embedded substrate, temperature-cycling the chip-embedded substrate to induce solder reflow and define an input/output pin for each one of the at least two contacts, and machining the input/output pin for each one of the at least two contacts to extend exposed from the chip-embedded substrate to a common height within specification tolerance. Such a technique represents a paradigm shift in that the manufacturer of the chip-embedded substrate, as opposed to the immediate customer of the manufacturer, may assume the burden of quality control with respect to minimizing unintended solder void trapping under the input/output pins, thereby reinforcing existing customer loyalty and potentially attracting new customers.

Abstract: A method for manufacturing a thin film transistor is provided. The method comprises depositing sequentially a gate insulating layer and a gate metal layer on a semiconductor substrate; etching the gate metal layer uncovered by the first photoresist pattern; implementing a first ion implantation on the semiconductor substrate; etching a side wall of the first photoresist pattern; implementing a second ion implantation on the semiconductor substrate to form a source and a drain. The source and the drain include a heavily doped drain region and a lightly doped drain region.

Abstract: A sub-millimeter packaged microsystem includes a microsystem located in a sealed cavity defined between first and second portions of a micropackage. One or both micropackage portions can be fabricated from a metal suitable for use in a harsh environment, such as an oil well environment. The microsystem includes electronic components and can be configured to communicate with external components through a wall of the micropackage by wireless communication or by conductive feedthroughs. Pluralities of microsystems, first micropackage portions, and/or second micropackage portions are simultaneously placed during a batch assembly process. The assembly process may include micro-crimping the first and second micropackaging portions together without the need for bonding materials and related process steps.

Abstract: A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x?0.2, and having a pH less than or equal to 1.5.

Abstract: Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a single lithography step whereby the need for alignment and overlay in the process is completely eliminated thereby enabling near-zero overlay error. Furthermore, techniques are developed to use these methods to fabricate self-aligned nanoscale multi-level/multi-height patterns with various shapes for master templates, replica templates and nanoimprint based pattern replication. Furthermore, the templates can be used to pattern multiple levels in a sacrificial polymer resist and achieve pattern transfer of the levels into a variety of substrates to form completed large area nanoelectronic and nanophotonic devices using only one patterning step.

Abstract: A manufacturing method of display with lighting devices is disclosed, including providing a tank containing a liquid; disposing a carrying plate with several recessed regions in the tank, and the carrying plate being immersed in the liquid; dropping several lighting devices into the liquid, wherein each of the lighting devices includes two conductive pads, and one of the two conductive pads includes a magnetic material; applying a magnetic field for the lighting devices and the lighting devices will dispose within the recessed regions of the carrying plate; removing the carrying plate with the lighting devices out of the tank, and assembling the lighting devices to an array substrate.

Abstract: A wafer has a device area on one side with a plurality of devices partitioned by a plurality of division lines. Either side of the wafer is attached to an adhesive tape supported by a first annular frame. A modified region is formed in the wafer along the division lines by a laser. The wafer is placed on a support member whose outer diameter is smaller than an inner diameter of the first annular frame. After applying the laser beam, the adhesive tape is expanded thereby dividing the wafer along the division lines. A second annular frame is attached to a portion of the expanded adhesive tape. An inner diameter of the second annular frame is smaller than the outer diameter of the support member and smaller than the inner diameter of the first annular frame.

Abstract: The invention relates in particular to a method for producing subsequent patterns in an underlying layer (120), the method comprising at least one step of producing prior patterns in a carbon imprintable layer (110) on top of the underlying layer (120), the production of the prior patterns involving nanoimprinting of the imprintable layer (110) and leave in place a continuous layer formed by the imprintable layer (110) and covering the underlying layer (120), characterized in that it comprises the following step: at least one step of modifying the underlying layer (120) via ion implantation (421) in the underlying layer (120), the implantation (421) being carried out through the imprintable layer (110) comprising the subsequent patterns, the parameters of the implantation (421) being chosen in such a way as to form, in the underlying layer (120), implanted zones (122) and non-implanted zones, the non-Implanted zones defining the subsequent patterns and having a geometry that is dependent on the prior pattern

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.

Abstract: A method of forming a thin film includes forming an interface layer stack on a semiconductor substrate. Forming the interface layer stack may include performing a first surface treatment on the semiconductor substrate under a reducing atmosphere. Forming the interface layer stack may include performing a second surface treatment on the semiconductor substrate. The first surface treatment may be performed under a reducing atmosphere and the second surface treatment may be performed under a nitridation atmosphere. The first surface treatment may include forming a lower interface layer on a surface of the semiconductor substrate and the second surface treatment may include forming an upper interface layer. The first surface treatment may include selectively removing at least one oxide material from a native oxide film on the semiconductor substrate.

Abstract: A method for producing a semiconductor device includes: depositing a barrier layer on a first surface of a semiconductor body having active regions of a semiconductor device; forming a contact layer that at least partially covers the barrier layer, the barrier layer being configured to prevent a material of the contact layer from diffusing into the semiconductor body; forming a first passivation layer on the contact layer and on exposed surfaces of the barrier layer; in a first etching process, removing the first passivation layer from above the barrier layer so as to uncover sections of the barrier layer; and in a second etching process, removing at least some sections of the barrier layer uncovered by the first etching process

Abstract: The present invention relates to a support comprising: an electrically conductive biased table (10) connected to a high voltage power supply (12) and supported on an electrically insulating stand (40); an electrically insulating substrate carrier (20) in the form of a cylinder, its top face presenting a bearing plane designed to receive a substrate (50); legs (15) standing on the biased table (10) in order to support the bottom face of the substrate carrier (20); and at least one electrically conductive connection (201, 202, 203, 31, 30) for connecting the bearing plane to the biased table (10). The support is remarkable in that the substrate carrier (20) incorporates a heating resistance (26).

Abstract: Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

Abstract: A semiconductor device includes a substrate, light sensing devices, at least one infrared radiation sensing device, a transparent insulating layer, an infrared radiation cut layer, a color filter layer and an infrared radiation color filter layer. The light sensing devices and the at least one infrared radiation sensing device are disposed in the substrate and are adjacent to each other. The transparent insulating layer is disposed on the substrate overlying the light sensing devices and the at least one infrared radiation sensing device. The infrared radiation cut layer is disposed on the transparent insulating layer overlying the light sensing devices for filtering out infrared radiation and/or near infrared radiation. The color filter layer is disposed on the infrared radiation cut layer. The infrared radiation color filter layer is disposed on the transparent insulating layer overlying the at least one infrared radiation sensing device.

Abstract: In a method of manufacturing a quantum dot, a core may be formed using (utilizing) at least one cation precursor and at least one anion precursor. The core may be reacted with a shell forming precursor and a ligand forming precursor for more than one hour to form a shell enclosing the core and a ligand. A nanoparticle including the core, the shell and the ligand may be washed.

Abstract: Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.

Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.