Abstract: A semiconductor package may include a redistribution substrate, a semiconductor chip mounted on a top surface of the redistribution substrate, and a conductive terminal provided on a bottom surface of the redistribution substrate. The redistribution substrate may include an under-bump pattern including a via portion in contact with the conductive terminal and a wire portion on the via portion and an insulating layer covering top and side surfaces of the under-bump pattern. A central portion of a bottom surface of the via portion may be provided at a level higher than an edge portion of the bottom surface of the via portion.

Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, an isolator includes a leadframe having first and second die paddles each having opposed first and second surfaces, a first die supported by the first surface of the first die paddle, and a second die supported by the first surface of the second die paddle. The first and second die paddles are configured enhanced creepage characteristics.

Abstract: A semiconductor device includes a substrate having a semiconductor fin. A gate structure is over the semiconductor fin, in which the gate structure has a tapered profile and comprises a gate dielectric. A work function metal layer is over the gate dielectric, and a filling metal is over the work function metal layer. A gate spacer is along a sidewall of the gate structure, in which the work function metal layer is in contact with the gate dielectric and a top portion of the gate spacer. An epitaxy structure is over the semiconductor fin.

Abstract: An optoelectronic device includes at least one primary sub-pixel having at least one first primary stack with at least two first main layers of indium nitride and gallium nitride, the layers separated in pairs at least by a first intermediate layer of gallium nitride. The device includes a first primary active layer with at least one first quantum well, and a second primary stack having at least two second main layers of indium nitride and gallium nitride the layers separated in pairs by a second intermediate layer of gallium nitride; at least one second primary active layer with one second quantum well; and a first primary junction layer formed on and in contact with the second primary active layer, the first primary junction layer doped according to a second type of doping chosen from an N-type and a P-type dopings, the second type of doping different from the first type.

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, and a semiconductor device. The interposer substrate is disposed over the package substrate, wherein the interposer substrate has a bottom surface facing the package substrate and a first cavity formed on the bottom surface. The semiconductor device is disposed in the first cavity. The package substrate has a top surface facing the interposer substrate and a second cavity formed on the top surface, wherein the second cavity is configured to accommodate the semiconductor device.

Abstract: Semiconductor die assemblies with decomposable materials, and associated methods and systems are disclosed. In an embodiment, a semiconductor die assembly includes a memory controller die carrying one or more memory dies attached to its first side. The semiconductor die assembly also includes a biodegradable structure attached to its second side opposite to the first side. The biodegradable structure includes a conductive material and an insulating material, both of which are biodegradable and disintegrate in a wet process. The biodegradable structure can be configured to couple the memory controller die with an interface die. In this manner, when the biodegradable structure disintegrates (e.g., dissolve) in the wet process, the memory controller carrying the memory dies can be separated from the interface die to reclaim the memory controller with the memory dies and the interface die.

Abstract: A wafer system-level three-dimensional fan-out packaging structure and a manufacturing method therefor. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and a second surface opposite to each other; forming a conductive connecting post on the second surface of the redistribution layer; bonding the patch element to the second surface of the redistribution layer; forming a plastic packaging layer on the second surface of the redistribution layer; thinning the plastic packaging layer; forming a plurality of solder bumps on a side of the plastic packaging layer that faces away from the redistribution layer; cutting the redistribution layer and the plastic packaging layer to obtain a number of first package structures; and bonding a second package layer to the first surface of the redistribution layer of one of the first package structures.

Abstract: A semiconductor package includes a package substrate, an interposer on the package substrate, semiconductor devices in individual mounting regions on a first surface of the interposer, respectively, first conductive connection members, and a molding member on the interposer. The interposer has first bonding pads in the individual mounting regions, respectively. The semiconductor devices each have chip pads electrically connected to the first bonding pads. The first conductive connection members are between the first bonding pads and the chip pads. The molding member covers the semiconductor devices and fills gaps between the first surface of the interposer and the semiconductor devices. At least one of the individual mounting regions includes a pad-free region with a cross shape and pad regions defined by the pad-free region, and the first bonding pads are in the pad regions.

Abstract: A system-in-package chip of printer driver system applicable in a printer includes a first chip, a second chip, and a third chip. The first chip, the second chip, and the third chip are arranged in a common package. The first chip and the second chip are arranged side-by-side on a carrier in the common package. The third chip is arranged on a top portion of the first chip in the common package. A wire carrier structure is formed on the top portion of the first chip before the third chip is disposed on the first chip.

Abstract: A light emitting element includes a substrate and a first light emitting part and a second light emitting part arranged thereon to emit different colored lights. The first light emitting part includes a first laminate structure where a n-type semiconductor film and a first semiconductor film are laminated, a first capping film and a p-type semiconductor film laminated on the first laminate structure. The second light emitting part includes a second laminate structure where the n-type semiconductor film, the first semiconductor film, a first intermediate film, and a second semiconductor film are laminated, a second capping film and the p-type semiconductor film laminated on the second laminate structure, the first capping film being the first intermediate film. A bandgap of the first intermediate film is higher than the first semiconductor film and the second semiconductor film. The bandgap of the second semiconductor film is lower than the first semiconductor film.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate stack on the first region and including a first gate stacked insulating film and a first gate electrode on the first gate stacked insulating film, and a second gate stack on the second region and including a second gate stacked insulating film and a second gate electrode on the second gate stacked insulating film, wherein a width of the first gate stack is greater than a width of the second gate stack and the second gate stacked insulating film includes a plurality of ferroelectric material films.

Abstract: A method of fabricating a bridged multi-chip assembly structure includes providing a carrier substrate. The method further includes arranging a plurality of chips on the carrier substrate in a predetermined layout. Each chip has a front surface including a set of terminals formed thereon. The method further includes depositing a molding material between the plurality of chips and on the carrier substrate. The method further includes removing the carrier substrate from the plurality of chips fixed by the molding material. The method further includes bonding a bridge chip to corresponding sets of terminals of at least two chips of the plurality of chips fixed by the molding material.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

Abstract: Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a platform has an upper surface and a lower surface opposite the upper surface and has a ground plane. A microelectronic device is coupled to the upper surface of the platform. Wire bond wires are coupled to the ground plane with a pitch. The wire bond wires extend away from the upper surface of the platform with upper ends of the wire bond wires extending above an upper surface of the microelectronic device. The wire bond wires are spaced apart from one another to provide a fence-like perimeter to provide an interference shielding cage. A conductive layer is coupled to at least a subset of the upper ends of the wire bond wires for electrical conductivity to provide a conductive shielding layer to cover the interference shielding cage.

Abstract: A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, a heat dissipation structure on the package substrate, the heat dissipation structure including a center portion and an edge portion, a dam structure on a bottom surface of the center portion of the heat dissipation structure, the dam structure on a top surface of the semiconductor chip, and a heat conductive layer between the center portion of the heat dissipation structure and the semiconductor chip. A top surface of the dam structure is located at a same distance from a top surface of the package substrate in a vertical direction as a top surface of the heat conductive layer, wherein the vertical direction is perpendicular to the top surface of the package substrate.

Abstract: A compound semiconductor device, a compound semiconductor substrate, and a method for manufacturing of a compound semiconductor device. Compound semiconductor device 100 comprises Si substrate 1 which has a shape surrounding hole 21 when viewed in a plane, SIC layer 3 formed on top surface 1a of Si substrate 1 and covers hole 21, nitride layer 10 containing Ga formed on the top surface side of SiC layer 3, source electrode 13, drain electrode 15, and gate electrode 17 formed on the top surface side of nitride layer 10. The current flowing between source electrode 13 and drain electrode 15 can be controlled by the voltage applied to gate electrode 17. The Si substrate does not exist in the area RG where source electrode 13, drain electrode 15, and gate electrode 17 overlap the area when viewed from the direction orthogonal to top surface 1a of Si substrate 1.

Abstract: In an embodiment, a method includes: bonding a back side of a first memory device to a front side of a second memory device with dielectric-to-dielectric bonds and with metal-to-metal bonds; after the bonding, forming first conductive bumps through a first dielectric layer at a front side of the first memory device, the first conductive bumps raised from a major surface of the first dielectric layer; testing the first memory device and the second memory device using the first conductive bumps; and after the testing, attaching a logic device to the first conductive bumps with reflowable connectors.